{"id":184009,"updated":"2025-01-20T03:26:20.320112+00:00","links":{},"created":"2025-01-19T00:51:29.361013+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00184009","sets":["1164:2822:9120:9274"]},"path":["9274"],"owner":"11","recid":"184009","title":["多数決関数を用いた並列プレフィックス加算器の実現と最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-30"},"_buckets":{"deposit":"45257197-cf69-4a13-8902-e09a2a1baef3"},"_deposit":{"id":"184009","pid":{"type":"depid","value":"184009","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"多数決関数を用いた並列プレフィックス加算器の実現と最適化","author_link":["405510","405508","405512","405511","405513","405509"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"多数決関数を用いた並列プレフィックス加算器の実現と最適化"},{"subitem_title":"Implementation and Optimization of Parallel Prefix Adders Using Majority Function","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計最適化手法","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2017-10-30","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/184009/files/IPSJ-EMB17046021.pdf","label":"IPSJ-EMB17046021.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB17046021.pdf","filesize":[{"value":"628.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1dfffebc-3ba2-47e4-a26c-345ed8b0b7e8","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"松本, 大輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"木村, 晋二"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Daiki, Matsumoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinji, Kimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年の FPGA やポスト CMOS デバイスでは，3 入力の多数決演算を効率よく実現でき，3 入力の多数決演算に基づく回路構成法が盛んに研究されている．これまで加算器等で素子削減が報告されていたが，具体的な構成法は示されていなかった．ここでは，プレフィックスグラフで表された加算回路を多数決演算でシステマティックに実現する手法と，桁上げ生成の性質を用いた多数決素子数削減手法を示している．提案削減手法で，プレフィックスグラフをシステマティックに実現する場合と比較して素子数および電力遅延積の削減を達成した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration methods based on three-input majority operation are widely studied. Element reduction has been reported on adders and so on, but the precise construction method has not been shown. This manuscript shows a method of systematically realizing parallel prefix adders using majority operations and a method of reducing majority operations using the property of carry propagation. By the proposed reduction method, we achieved reduction of the number of majority operations and the power delay product as compared with the systematic realization of parallel prefix adders.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2017-10-30","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"21","bibliographicVolumeNumber":"2017-EMB-46"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}