{"updated":"2025-01-20T03:27:18.416052+00:00","links":{},"id":183950,"created":"2025-01-19T00:51:26.020437+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183950","sets":["1164:2036:9049:9273"]},"path":["9273"],"owner":"11","recid":"183950","title":["ツインタワー用共有メモリチップの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-30"},"_buckets":{"deposit":"acde6baf-84c2-4acb-aa50-738eae6602ef"},"_deposit":{"id":"183950","pid":{"type":"depid","value":"183950","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ツインタワー用共有メモリチップの開発","author_link":["405123","405121","405127","405125","405128","405122","405124","405118","405130","405119","405120","405129","405126","405131"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ツインタワー用共有メモリチップの開発"},{"subitem_title":"A shared memory chip for twin-tower of chips","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路実装技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2017-10-30","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"東京農工大学工学研究院"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183950/files/IPSJ-SLDM17181009.pdf","label":"IPSJ-SLDM17181009.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM17181009.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"4d5afd06-4e9a-4dca-8fa1-765d13de348b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"寺嶋, 爽花"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"奥原, 颯"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松下, 悠亮"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"安藤, 尚輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"並木, 美太郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Sayaka, Terashima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Kojima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hayate, Okuhara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yusuke, Matsushita","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoki Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Mitaro, Namiiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ビルディングブロック型計算システムにおいて，誘導結合チップ間無線結合インタフェース TCI を用いて 2 つのチップ積層間に共有メモリを実現する SMTT (Shared Memory for Twin Tower) チップを開発した．SMTT をこの積層ブロック間の橋として配置することで，ツインタワーのような一つの SiP を実装することが可能である．本稿では SMTT によるツインタワーアーキテクチャと共有メモリによるアプリケーションの並列化について述べる．シミュレーションの結果，ツインタワー型のシステムでは従来のビルディングブロック型計算システムと比べて，約 35% の性能の向上が得られることが分かった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A shared memory chip for the building-block computing system using ThruChip Interface (TCI) is developed and evaluated. The implemented memory chip can connect two blocks of 3-D stacked chip blocks via TCI. Hence, using it as a bridge between these two blocks, a new 3-D integration System in a Package (SiP) which has twin-towers of chips can be realized. In this report, we reveal an architecture of the twin-tower for a SiP and evaluate its performance improvement. In our evaluation, the twin-tower system can improve 35% of system performance when compared to the conventional building-block computing system.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2017-10-30","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"9","bibliographicVolumeNumber":"2017-SLDM-181"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}