{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183868","sets":["1164:1579:9047:9270"]},"path":["9270"],"owner":"11","recid":"183868","title":["情報落ちを考盧した短ピット長フォーマットによるDCNNトレーニングの検討\\n\\n"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-31"},"_buckets":{"deposit":"90ac74ba-7281-45cc-837f-13ef0884e921"},"_deposit":{"id":"183868","pid":{"type":"depid","value":"183868","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"情報落ちを考盧した短ピット長フォーマットによるDCNNトレーニングの検討\\n\\n","author_link":["404699","404703","404698","404702","404701","404700"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"情報落ちを考盧した短ピット長フォーマットによるDCNNトレーニングの検討\\n\\n"},{"subitem_title":"DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"機械学習","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2017-10-31","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"産業技術総合研究所ナノエレクトロニクス研究部門"},{"subitem_text_value":"産業技術総合研究所ナノエレクトロニクス研究部門"},{"subitem_text_value":"産業技術総合研究所情報技術部門"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nanoelectronics Research Institute and National Institute of AIST","subitem_text_language":"en"},{"subitem_text_value":"Nanoelectronics Research Institute and National Institute of AIST","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Research Institute, National Institute of AIST,","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183868/files/IPSJ-ARC17228002.pdf","label":"IPSJ-ARC17228002.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC17228002.pdf","filesize":[{"value":"775.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"92d3feb6-ccd9-4ef2-b292-32e28b1edd8f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大内, 真一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"更田, 裕司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高野, 了成"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shin-ichi, O'uchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Fuketa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryousei, Takano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"16 ビットよりも更に短いビット長のフォーマットによる深層畳み込みニューラルネットワークのトレーニングを実現するために，本論文では計算における情報落ちに関して検討する．検討の結果として，8 ビットフォーマットによるトレーニング方法を提案する．提案方式は，16 ビット積和算ユニットに対して，約 1/2 のハードウェア削減効果を持ちつつも，AlexNet のトレーニングにおいて 16 ビット浮動小数点フォーマットを上回る推論精度改善が期待される．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Loss of trailing digits in training deep convolutional neural network (DCNN) is considered to implement training with a format shorter than 16-bit floating format. As a result, we propose an 8-bit training method. The method improves inference accuracy compared to 16-bit floating format in training AlexNet. Simultaneously, the hardware size is reduced by half compared to the 16-bit hardware.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2017-10-31","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"2017-ARC-228"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":183868,"updated":"2025-01-20T03:29:48.543727+00:00","links":{},"created":"2025-01-19T00:51:21.477406+00:00"}