Bus Serialization for Reducing Power Consumption

• Item type: Trans(1)
• 公開日: 2006-03-15
• タイトル: Bus Serialization for Reducing Power Consumption
• タイトル / 言語: en
• タイトル: Bus Serialization for Reducing Power Consumption
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: プロセッサアーキテクチャ
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science and Technology the University of Tokyo
• 著者所属: Texas Instruments Japan Ltd.
• 著者所属: School of Law the University of Tokyo
• 著者所属: Graduate School of Information Science and Technology the University of Tokyo
• 著者所属: Hitachi Ltd
• 著者所属: Graduate School of Information Science and Technology the University of Tokyo
• 著者所属: Institute of Information Security
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, the University of Tokyo
• 著者所属(英): en
• 著者所属(英): Texas Instruments Japan, Ltd.
• 著者所属(英): en
• 著者所属(英): School of Law, the University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, the University of Tokyo
• 著者所属(英): en
• 著者所属(英): Hitachi, Ltd
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, the University of Tokyo
• 著者所属(英): en
• 著者所属(英): Institute of Information Security
• 著者名: Naoya, Hatta; NikoDemusBarli; Chitaka, Iwama; LuongDinhHung; Daisuke, Tashiro; Shuichi, Sakai; Hidehiko, Tanaka
• 著者名(英): Naoya, Hatta; Niko, DemusBarli; Chitaka, Iwama; Luong, DinhHung; Daisuke, Tashiro; Shuichi, Sakai; Hidehiko, Tanaka
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45nm technology process.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45nm technology process.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11833852
• 書誌情報: 情報処理学会論文誌コンピューティングシステム（ACS）; 巻 47, 号 SIG3(ACS13), p. 49-57, 発行日 2006-03-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7829
• 出版者 / 言語: ja
• 出版者: 情報処理学会