{"created":"2025-01-19T00:50:49.504991+00:00","updated":"2025-01-20T03:44:41.455427+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183287","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183287","title":["遅延変動に対しロバストなAES暗号回路の設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"3a92d739-145f-41b5-8eb8-5e1a3ed31bc2"},"_deposit":{"id":"183287","pid":{"type":"depid","value":"183287","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"遅延変動に対しロバストなAES暗号回路の設計","author_link":["401806","401805","401807"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"遅延変動に対しロバストなAES暗号回路の設計"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183287/files/IPSJ-DAS2017040.pdf","label":"IPSJ-DAS2017040.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017040.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"547e7ff2-b4f2-465a-bd4a-cebfed8a20de","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"矢作, 裕基"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年の半導体技術の発展に伴い，回路設計の複雑化と遅延ばらつきの増大による，タイミングエラー発生のリスクが高まりつつある．従来のワーストケース設計に代わるタイミングエラー対策手法のひとつに STEP がある．STEP はパスの途中の信号遷移を監視することによりタイミングエラーを予測する．予測後はクロックゲーティングによりタイミングエラーを回避する．本稿では STEP を AES 暗号回路に適用することで，遅延変動に対してロバストな AES 暗号回路を提案する．提案する AES 暗号回路は，回路モジュールの分割点を STEP 挿入位置とすることで，遅延が十分に短くタイミングエラー発生が無視できるパスを除く全てのパスを網羅的に STEP で監視し，回路全体で起こるタイミングエラーの予測とクロックゲーティングを用いたタイミングエラーの回避ができ，その結果遅延ばらつきが生じた場合でも正しく動作することができる．実験結果から提案する AES 暗号回路は STEP を導入しない設計に対して，8.05 % の面積オーバーヘッドで AES 暗号回路を監視し，最大動作周波数を 1.66 倍に向上させることができた．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"215","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"210","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":183287,"links":{}}