{"updated":"2025-01-20T03:44:37.492581+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183283","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183283","title":["フリップフロップ組合せの状態正当化による到達不能状態を用いた順序回路のテスト不能故障判定法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"eab5d85c-73a6-4d60-8ff3-6693d75a0385"},"_deposit":{"id":"183283","pid":{"type":"depid","value":"183283","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"フリップフロップ組合せの状態正当化による到達不能状態を用いた順序回路のテスト不能故障判定法","author_link":["401781","401779","401777","401785","401780","401786","401778","401788","401783","401782","401784","401787","401775","401776"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"フリップフロップ組合せの状態正当化による到達不能状態を用いた順序回路のテスト不能故障判定法"},{"subitem_title":"An Untestable Fault Identification Method for Sequential Circuits Using Unreachable States by Justification of State Cubes","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"信頼性・ばらつき","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本大学大学院生産工学研究科"},{"subitem_text_value":"日本大学生産工学部"},{"subitem_text_value":"京都産業大学コンピュータ理工学部"},{"subitem_text_value":"日本大学生産工学部"},{"subitem_text_value":"日本大学生産工学部"},{"subitem_text_value":"徳島大学大学院社会産業理工学研究部"},{"subitem_text_value":"徳島大学大学院社会産業理工学研究部"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"College of Faculty of Computer Science and Engineering, Kyoto Sangyo University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology, Industrial and Social Sciences, Tokushima University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology, Industrial and Social Sciences, Tokushima University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183283/files/IPSJ-DAS2017036.pdf","label":"IPSJ-DAS2017036.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017036.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"14cd7060-db79-4b44-85f8-273c9a78e73b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"二関, 森人"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"細川, 利典"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉村, 正義"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山崎, 紘史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"新井, 雅之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"四柳, 浩之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"橋爪, 正樹"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Morito, Niseki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Hosokawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Yoshimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Yamazaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayuki, Arai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroyuki, Yotsuyanagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaki, Hashizume","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"テストコストの削減やセキュリティ向上のため，スキャン設計を用いない非スキャン設計ベースのテストの要望がある．しかしながら，順序回路のテスト生成では，高い故障検出効率を得るために多大なテスト生成時間を要する．特にテスト不能故障判定時間が支配的である．そのため，テスト生成の前処理で，テスト不能故障を判定することが重要である．本論文では，SAT を用いて数個のフリップフロップ組合せの状態が到達不能状態か否かを判定し，その到達不能状態を用いたテスト不能故障判定法を提案する．また，既存の順序回路のテスト不能故障判定法と提案手法を組み合わせて，ISCAS' 89 及び ITC' 99 ベンチマーク回路においてテスト不能故障を判定し，評価する．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Non-scan based test generation is required for the purpose of resolving reduction of test cost and improvement of security. However, in the test generation of the sequential circuit, it consumes a lot of test generation time to obtain high fault efficiency. Especially, untestable fault identification time is dominant. Therefore, it is important to identify untestable faults in the pre-processing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Moreover, untestable faults are identified by applying the combination of conventional methods and our proposed method to ISCAS' 89 and ITC' 99 benchmark circuits, and the number of untestable faults is evaluated.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"191","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"186","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:50:49.289032+00:00","id":183283,"links":{}}