{"id":183282,"updated":"2025-01-20T03:44:36.350846+00:00","links":{},"created":"2025-01-19T00:50:49.235293+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183282","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183282","title":["セレクタ論理を適用したFFTプロセッサのFPGA実装評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"9f6ca06f-fcf0-44a6-b605-11d47598d721"},"_deposit":{"id":"183282","pid":{"type":"depid","value":"183282","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"セレクタ論理を適用したFFTプロセッサのFPGA実装評価","author_link":["401773","401771","401774","401772"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"セレクタ論理を適用したFFTプロセッサのFPGA実装評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"計算手法","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学理工学術院総合研究所"},{"subitem_text_value":"早稲田大学大学院基幹理工研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工研究科情報理工・情報通信専攻"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183282/files/IPSJ-DAS2017035.pdf","label":"IPSJ-DAS2017035.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017035.pdf","filesize":[{"value":"823.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"32e2d27e-54d5-4130-988d-53aaa83e4fcf","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"平井, 勇也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"高速フーリエ変換 （FFT） は信号処理に代表される様々なアプリケーションで利用されており，高速な FFT プロセッサを設計することが求められる．本稿では，FFT 中の差積演算 （減算後に乗算を行う演算） に着目した高速な FFT プロセッサの設計手法を提案する．差積演算にビットレベル式変形を施しセレクタ論理に帰着させることで桁上げ伝搬遅延を削減し，FFT プロセッサの処理速度向上を図る．本設計手法では，遅延時間の大きな差積演算のみをセレクタ論理に帰着させることで必要なハードウェア資源を抑えた設計を可能にする．差積演算の一部をセレクタ論理に帰着させた FFT プロセッサを FPGA に実装した結果，通常の FFT プロセッサに比べ，処理速度を最大 21 % 向上するとともに，LUT 数を最大 33 % 削減できることを確認した．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"185","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"180","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}