{"id":183260,"updated":"2025-01-20T03:44:08.415470+00:00","links":{},"created":"2025-01-19T00:50:48.041142+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183260","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183260","title":["高ポイント高速数論変換に対する高位合成のためのループ構造最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"e6143db6-36e3-42a2-8775-2355c7a0ad7d"},"_deposit":{"id":"183260","pid":{"type":"depid","value":"183260","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"高ポイント高速数論変換に対する高位合成のためのループ構造最適化","author_link":["401661","401660","401659"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高ポイント高速数論変換に対する高位合成のためのループ構造最適化"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学術院総合研究所"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183260/files/IPSJ-DAS2017013.pdf","label":"IPSJ-DAS2017013.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017013.pdf","filesize":[{"value":"845.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"529e5262-54bb-49a1-a2b4-0c697ad3d91d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"秘匿計算の実用化に向け，完全準同型暗号が注目を集めている．完全準同型暗号を用いた暗号文演算においては桁数の大きな乗算が多用され，演算時間のボトルネックとなる．高速数論変換を用いた乗算アルゴリズムにより桁数の大きな乗算を高速に実行可能であるが，高速数論変換処理の FPGA 実装によりさらなる高速化が期待される．実装にあたり，高位合成ツールを活用することでポイント数の大きな高速数論変換処理に対しても効率的なハードウェア設計が可能となる．本稿では，合成後ハードウェアの性能を最大限引き出すため，ソフトウェアコードに含まれるループ構造を二つの観点 （Loop flattening, Trip count reduction） で最適化する．ループ構造最適化を施した 65,536 ポイントの高速数論変換処理を高位合成し，FPGA 上に実装した結果，CPU での実行に比べ 6.9 倍高速化できることを確認した．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"68","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"63","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}