{"links":{},"id":183251,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183251","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183251","title":["ビアスイッチFPGAの性能予測モデル"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"bc362791-cd0e-44b6-9169-edc1cc988ad3"},"_deposit":{"id":"183251","pid":{"type":"depid","value":"183251","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ビアスイッチFPGAの性能予測モデル","author_link":["401562","401565","401561","401563","401560","401564"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ビアスイッチFPGAの性能予測モデル"},{"subitem_title":"A Model for Predicting Performance of Via-switch FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ビアスイッチFPGA","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183251/files/IPSJ-DAS2017004.pdf","label":"IPSJ-DAS2017004.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017004.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"3ad873a2-3e43-4cc0-b8b7-f408605f511a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"樋口, 達大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石原, 亨"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小野寺, 秀俊"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tatsuhiro, Higuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tohru, Ishihara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hidetoshi, Onodera","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA に代表される再構成可能回路は一般的に性能面で専用論理回路である ASIC に劣る．本稿ではビアスイッチと呼ばれるスイッチングデバイスを配線切り替えに用いた FPGA (Field Programmable Gate Array) の性能を予測するモデルについて述べる．ビアスイッチを FPGA の配線切り替えに用いることでチップの面積効率を向上させることができ，低電圧での性能低下を抑えることができる．ビアスイッチ FPGA の信号通過配線と論理回路のそれぞれについて遅延時間，消費エネルギー，面積をプロセスパラメータや回路構造でモデル化する．またそれらのモデルを用いてチップ全体の性能を回路シミュレーションなしに予測することができる．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Reconfigurable circuits are generally inferior to ASIC (application specific integrated circuit) in terms of performance. In this paper, we develop a model for predicting the performance of FPGA (Field Programmable Gate Array) which uses an emergining switching device called a Via-switch for wiring switching. By using the Via-switch, the chip area efficiency improves and the performance degradation of the circuit in low voltage region can be kept to the minimun. We model the delay, the energy consumption, and the area for wiring and logic circuit of Via-switch FPGA. The model uses process parameters and structure information of a targeting circuit as inputs. Moreover, with the model, it is possible to predict the performance of the entire chip without circuit simulation.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"14","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"9","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:50:47.553657+00:00","updated":"2025-01-20T03:43:55.800023+00:00"}