{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00183250","sets":["6164:6165:7651:9236"]},"path":["9236"],"owner":"11","recid":"183250","title":["ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-08-23"},"_buckets":{"deposit":"a109660b-5a44-488d-87cb-b98c7bf3726f"},"_deposit":{"id":"183250","pid":{"type":"depid","value":"183250","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証","author_link":["401558","401559"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ビアスイッチFPGA","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2017-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻／日本学術振興会"},{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/183250/files/IPSJ-DAS2017003.pdf","label":"IPSJ-DAS2017003.pdf"},"date":[{"dateType":"Available","dateValue":"2019-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2017003.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"cf1308f6-fe69-4452-84b9-688603b93c1f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"土井, 龍太郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"橋本, 昌宜"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"従来 FPGA の性能ボトルネックである SRAM 型スイッチを，不揮発性メモリの一種であるビアスイッチで置換した FPGA に関する研究 ・ 開発が行われている．ビアスイッチ FPGA は縦と横に走る信号配線の交点にビアスイッチを配置したクロスバー回路により配線接続の切り換えを実現する．しかし，スイッチのプログラミングに共用の信号配線を使用するため，回路のプログラミング状態によっては，プログラミング信号が回り込んで意図しないスイッチに与えられるスニークパス問題が生じる．本稿では，FPGA の正常な再構成を阻害するスニークパス問題について，SAT 符号化を利用した数学的な検証に取り組む．回路動作などを論理式で表現し，SAT ソルバにより検証した結果，適切なオペレーション制約下での FPGA 運用によりスニークパス問題が回避できることがわかった．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2017論文集"}],"bibliographicPageStart":"3","bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2017"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":183250,"updated":"2025-01-20T03:43:54.665006+00:00","links":{},"created":"2025-01-19T00:50:47.499707+00:00"}