{"created":"2025-01-18T22:51:04.131688+00:00","updated":"2025-01-22T22:50:45.909560+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00018297","sets":["934:1119:1131:1133"]},"path":["1133"],"owner":"1","recid":"18297","title":["マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-09-15"},"_buckets":{"deposit":"a0540561-c92f-4f12-983d-2f784f5be021"},"_deposit":{"id":"18297","pid":{"type":"depid","value":"18297","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法"},{"subitem_title":"Compiler Control Power Saving Scheme for Multicore Processors","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2006-09-15","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科"},{"subitem_text_value":"アドバンストチップマルチプロセッサ研究所"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科，アドバンストチップマルチプロセッサ研究所"},{"subitem_text_value":"早稲田大学理工学部コンピュータ・ネットワーク工学科，アドバンストチップマルチプロセッサ研究所"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Advanced Chip Multiprocessor Research Institute","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University , Advanced Chip Multiprocessor Research Institute","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Waseda University , Advanced Chip Multiprocessor Research Institute","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/18297/files/IPSJ-TACS4712013.pdf"},"date":[{"dateType":"Available","dateValue":"2008-09-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS4712013.pdf","filesize":[{"value":"460.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3cd00547-768d-426e-b152-660aa7038a85","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2006 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"白子, 準"},{"creatorName":"吉田, 宗弘"},{"creatorName":"押山, 直人"},{"creatorName":"和田, 康孝"},{"creatorName":"中野, 浩史"},{"creatorName":"鹿野, 裕明"},{"creatorName":"木村, 啓二"},{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, Shirako","creatorNameLang":"en"},{"creatorName":"Munehiro, Yoshida","creatorNameLang":"en"},{"creatorName":"Naoto, Oshiyama","creatorNameLang":"en"},{"creatorName":"Yasutaka, Wada","creatorNameLang":"en"},{"creatorName":"Nakano, Hirofumi","creatorNameLang":"en"},{"creatorName":"Hiroaki, Shikano","creatorNameLang":"en"},{"creatorName":"Keiji, Kimura","creatorNameLang":"en"},{"creatorName":"Hironori, Kasahara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体集積度の向上にともなう消費電力の増大，集積トランジスタ数の増化に対する処理性能向上の鈍化に対処するため，チップ上に複数のプロセッサを集積するマルチコアアーキテクチャ（チップマルチプロセッサ）が大きな注目を集めている．このようなマルチコアアーキテクチャの能力を最大限に引き出し，高実効性能・低消費電力を達成するためには，プログラムの適切な並列化に加えチップ上のリソースのきめ細かな電圧・動作周波数制御を実現するコンパイラが必要不可欠である．本論文では，各プロセッサコアが等価であるOSCARタイプのマルチコアプロセッサにおいて，各プロセッサの電源のON/OFF・周波数電圧制御（FV制御）をマルチグレイン並列化環境下でコンパイラが適切に判断し低消費電力化を行うコンパイル手法を提案する．提案手法を実装したOSCARコンパイラにより，科学技術計算とマルチメディアアプリケーションに対する評価を行った結果，SPEC CFP95 appluにおいて4プロセッサ使用時に最小実行時間を維持したまま60.7%の消費エネルギー削減，MPEG2エンコーダにおいて4プロセッサ使用時にデッドライン制約を保証したまま82.7%の消費エネルギー削減が達成された．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A chip multiprocessor architecture has attracted much attention to achieve high effective performance and to save the power consumption, with the increase of transistors integrated onto a chip. To this end, the compiler is required not only to parallelize program effectively, but also to control the volatage and clock frequency of computing resources carefully. This paper proposes a power saving compiling scheme with the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each core on the multiprocessor. In the evaluation, OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu using 4 processors without performance degradation, and 82.7 percent energy savings for MPEG2 encoder using 4 processors added deadline constraint.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"158","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"147","bibliographicIssueDates":{"bibliographicIssueDate":"2006-09-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"SIG12(ACS15)","bibliographicVolumeNumber":"47"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":18297,"links":{}}