Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access

• Item type: Trans(1)
• 公開日: 2006-11-15
• タイトル: Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access
• タイトル / 言語: en
• タイトル: Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: プロセッサアーキテクチャ
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者名: LuongDinhHung; Masahiro, Goshima; Shuichi, Sakai
• 著者名(英): Luong, DinhHung; Masahiro, Goshima; Shuichi, Sakai
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Error Correction Code (ECC) is widely used to detect and correct soft errors in VLSI caches. Maintaining ECC on a per-word basis which is preferable in caches with word-based access is expensive. This paper proposes Zigzag-HVP a cost-effective technique to detect and correct soft errors in such caches. Zigzag-HVP utilizes horizontal-vertical parity (HVP). HVP maintains the parity of a data array both horizontally and vertically. Basic HVP can detect and correct a single bit error (SBE) but not a multi-bit error (MBE). By dividing the data array into multiple HVP domains and interleaving bits of different domains a spatial MBE can be converted to multiple SBEs each of which can be detected and corrected by the corresponding parity domain. Vertical parity updates and error recovery in Zigzag-HVP can be efficiently executed through modifications to the cache data paths write-buffer and Built-In Self Test. The evaluation results indicate that the area and power overheads of Zigzag-HVP caches are lower than those of ECC-based ones.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Error Correction Code (ECC) is widely used to detect and correct soft errors in VLSI caches. Maintaining ECC on a per-word basis, which is preferable in caches with word-based access, is expensive. This paper proposes Zigzag-HVP, a cost-effective technique to detect and correct soft errors in such caches. Zigzag-HVP utilizes horizontal-vertical parity (HVP). HVP maintains the parity of a data array both horizontally and vertically. Basic HVP can detect and correct a single bit error (SBE), but not a multi-bit error (MBE). By dividing the data array into multiple HVP domains and interleaving bits of different domains, a spatial MBE can be converted to multiple SBEs, each of which can be detected and corrected by the corresponding parity domain. Vertical parity updates and error recovery in Zigzag-HVP can be efficiently executed through modifications to the cache data paths, write-buffer, and Built-In Self Test. The evaluation results indicate that the area and power overheads of Zigzag-HVP caches are lower than those of ECC-based ones.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11833852
• 書誌情報: 情報処理学会論文誌コンピューティングシステム（ACS）; 巻 47, 号 SIG18(ACS16), p. 44-54, 発行日 2006-11-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7829
• 出版者 / 言語: ja
• 出版者: 情報処理学会