{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00178690","sets":["1164:2036:9049:9152"]},"path":["9152"],"owner":"11","recid":"178690","title":["隣接するブロック間のみに配線をもつFPGAに対する配置配線手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-05-03"},"_buckets":{"deposit":"e56b5419-45d5-4505-bcf6-be73c971cfa1"},"_deposit":{"id":"178690","pid":{"type":"depid","value":"178690","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"隣接するブロック間のみに配線をもつFPGAに対する配置配線手法","author_link":["383426","383425","383424","383427"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"隣接するブロック間のみに配線をもつFPGAに対する配置配線手法"},{"subitem_title":"Mapping and routing method for the FPGA which has wires between only neighbor blocks","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"物理・レイアウト設計","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2017-05-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大規模集積システム設計教育研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic Engineering, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design and Education Center, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/178690/files/IPSJ-SLDM17180005.pdf","label":"IPSJ-SLDM17180005.pdf"},"date":[{"dateType":"Available","dateValue":"2019-05-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM17180005.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"27282d68-fce5-4df7-b832-a09f57bdca45","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"丸岡, 大浩"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤田, 昌宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomohiro, Maruoka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Fujita","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA の集積度が増すにつれ，FPGA の低コスト化と高速化が進んだ一方でタイミングクロージャ問題が大きな課題となっている．そこでタイミングクロージャ問題が原理的に生じないようにするため，隣接する論理ブロック間のみに配線を持つ FPGA のモデルについて検討した．本論文では配置配線の際の制約を整数線形計画問題 （ILP） として定式化することにより配置配線を行う手法を提案し，実際にベンチマーク回路を用いてモデルの FPGA に対する配置配線が可能か否かを確かめた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2017-05-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2017-SLDM-180"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"updated":"2025-01-20T05:02:03.490506+00:00","created":"2025-01-19T00:48:00.563035+00:00","id":178690}