{"created":"2025-01-19T00:46:38.098417+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00177036","sets":["1164:2036:9049:9050"]},"path":["9050"],"owner":"11","recid":"177036","title":["新しい剰余SD数加算アルゴリズムとRSA暗号処理への応用"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-01-16"},"_buckets":{"deposit":"a0020fce-7f21-488d-b6ff-8894be9d74d5"},"_deposit":{"id":"177036","pid":{"type":"depid","value":"177036","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"新しい剰余SD数加算アルゴリズムとRSA暗号処理への応用","author_link":["374847","374848","374843","374846","374845","374844"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"新しい剰余SD数加算アルゴリズムとRSA暗号処理への応用"},{"subitem_title":"A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"専用システムとアクセラレータ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2017-01-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"},{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"},{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Gimma University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Gimma University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Gimma University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/177036/files/IPSJ-SLDM17178026.pdf","label":"IPSJ-SLDM17178026.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM17178026.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"b534c170-2a90-42ba-a31c-02cd5cc0e4b4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2017 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"石川, 和誠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田中, 勇樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"魏, 書剛"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazumasa, Ishikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuuki, Tanaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shugang, Wei","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，長い語長を有する剰余算術演算のため，SD (Signed - Digit) 数を用いた新しい剰余加算アルゴリズムを提案する．本提案のアルゴリズムでは，従来の剰余演算に用いられる法 m (2ⁿ-1<m<2ⁿ)の代わりに，剰余パラメータµ(=m-2ⁿ)を用いることで，n桁の剰余 SD 数加算を高速に行うことができる．そして，0.18µCMOS ゲートアレイ設計を前提とした剰余 SD 数加算器を内蔵した RSA 暗号処理プロセッサの構成を検討し，鍵のサイズを 2048 ビットとした場合でも，高速な暗号処理が実現できることを明らかにした．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such as RSA encryption with very long word-length. In the proposed algorithm, for the high-speed residue SD addition with n digits, a residue parameter : µ(= m — 2ⁿ) is used for the residue operation instead of using m(2ⁿ-1< m < 2ⁿ), which is the modulus in the residue arithmetic system. We apply the residue SD addition circuits to implement a RSA encryption processor by using a library with 0.18/µm CMOS VLSI technology. The design results show that high speed encryption can be achieved by using the proposed SD arithmetic architecture.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2017-01-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"26","bibliographicVolumeNumber":"2017-SLDM-178"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"links":{},"id":177036,"updated":"2025-01-20T05:38:38.170848+00:00"}