{"created":"2025-01-19T00:44:44.130892+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00174545","sets":["6164:6165:7651:8901"]},"path":["8901"],"owner":"11","recid":"174545","title":["電源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-09-07"},"_buckets":{"deposit":"7c2a4376-6113-4128-a77d-a3967222dc95"},"_deposit":{"id":"174545","pid":{"type":"depid","value":"174545","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"電源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案","author_link":["359753","359748","359751","359754","359750","359755","359752","359749"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"電源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案"},{"subitem_title":"An Efficient Clock-Gating Mechanism for Multi-Core Processor to reduce Power Supply Noise","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"システムレベル設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2016-09-07","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪大学大学院情報科学研究科"},{"subitem_text_value":"大阪大学大学院情報科学研究科"},{"subitem_text_value":"大阪大学大学院情報科学研究科"},{"subitem_text_value":"大阪大学大学院情報科学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Dept. Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Dept. Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Dept. Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/174545/files/IPSJ-DAS2016029.pdf","label":"IPSJ-DAS2016029.pdf"},"date":[{"dateType":"Available","dateValue":"2018-09-07"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2016029.pdf","filesize":[{"value":"1.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"95522412-b74c-415e-ae93-b6da8420ac07","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川部, 純"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"武内, 良典"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"劉, 載勲"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"今井, 正治"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, Kawabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshinori, Takeuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Jaehoon, Yu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaharu, Imai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"タスクの並列処理により高速化を達成するマルチコアプロセッサは消費電流の変化量が大きく，消費電流の変化が電源ノイズを大きくさせる原因となっている．電源ノイズはチップの誤動作を引き起こしプロセッサの信頼性を低下させる．本稿では消費電力の削減手法であるクロックゲーティングをコアに対して適用し，プロセッサの電流変化量を動的に抑制する機構を提案する．提案する機構により，プロセッサの性能低下を抑えつつ電流変化量を一定以下に保証する．実験により 4 コアマルチプロセッサの性能低下を最大 7%に抑えることを確認した．提案するクロックゲーティング機構により，性能低下が起きない条件下で，電流変化量を 2 ビット実装の場合 41.2%，3 ビット実装の場合 37.3%，4 ビット実装の場合 35.1%削減することを確認した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Multi-core processors achieve high performance by parallel processing of tasks. However, the large amount of current change of multi-core processors makes power supply noise large. Power supply noise causes low reliability of the processor. This paper proposes a mechanism which dynamically suppresses the amount of current change of the processor by controlling the execution of cores using clock-gating. The mechanism guarantees the amount of current change under certain level keeping performance. Evaluation results show that the performance degradation of 4 core multi-processor was within 7% by proposed mechanism, and amount of current change was reduced 41.2% by 2-bit implementation, 37.3% by 3-bit implementation, 35.1% by 4-bit implementation, respectively.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"156","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2016論文集"}],"bibliographicPageStart":"151","bibliographicIssueDates":{"bibliographicIssueDate":"2016-09-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"29","bibliographicVolumeNumber":"2016"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":174545,"updated":"2025-01-20T06:39:32.885612+00:00","links":{}}