{"updated":"2025-01-20T06:39:14.713435+00:00","links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00174533","sets":["6164:6165:7651:8901"]},"path":["8901"],"owner":"11","recid":"174533","title":["広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-09-07"},"_buckets":{"deposit":"2e4cd551-ea64-4b9b-9605-49c58bdebfdc"},"_deposit":{"id":"174533","pid":{"type":"depid","value":"174533","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ","author_link":["359668","359670","359667","359671","359669","359666"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ"},{"subitem_title":"An On-Chip Memory Enabling Minimum Energy Point Tracking over a Wide Operating Performance Range","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"省エネルギー","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2016-09-07","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/174533/files/IPSJ-DAS2016017.pdf","label":"IPSJ-DAS2016017.pdf"},"date":[{"dateType":"Available","dateValue":"2018-09-07"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2016017.pdf","filesize":[{"value":"2.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"95fb4d5e-ba4b-42e9-86ab-caeeb73bce35","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"塩見, 準"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石原, 亨"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小野寺, 秀俊"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, Shiomi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tohru, Ishihara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hidetoshi, Onodera","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"オンチップメモリはプロセッサの中で最もエネルギーを消費する素子の 1 つである．したがって，低消費エネルギー化のため電源電圧および基板電圧の調整がオンチップメモリにも適用されている．本稿では，65-nm FDSOI プロセスで製造されたオンチップメモリの測定結果を述べる．既存の 6T SRAM マクロと異なり，スタンダードセルベースメモリを使用することで，定格電圧から 0.3V のような幅広い動作性能領域で動作を可能にする．次に，オンチップメモリの電源電圧および基板電圧を同時に調整し，要求動作速度に対し消費エネルギーを最小化するエネルギー最小点でオンチップメモリを動作させる．DVFS 制御と比較して，最大 34%消費エネルギーを削減可能であることを示す．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"On-chip memory is one of the most energy consuming components in processors. Aggressive supply voltage scaling and adaptive body biasing are thus applied even to the on-chip memories. In this paper, an on-chip memory is designed to investigate a minimum energy point in a 65-nm FDSOI process technology. Unlike conventional on-chip memories, it employs standard-cell based memories (SCMs) as an alternative to conventional 6T SRAM macros, enabling it to operate at 0.3 V supply voltage. Then, simultaneous tuning of supply and threshold voltage is applied to the SCM, which enables it to operate with minimum energy consumption under a specific clock period. Measurement results show that the energy consumption of the SCM is reduced by 32% in comparison with the conventional DVFS technique.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"96","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2016論文集"}],"bibliographicPageStart":"91","bibliographicIssueDates":{"bibliographicIssueDate":"2016-09-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"17","bibliographicVolumeNumber":"2016"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":174533,"created":"2025-01-19T00:44:43.481937+00:00"}