@inproceedings{oai:ipsj.ixsq.nii.ac.jp:00174523,
 author = {増田, 豊 and 尾上, 孝雄 and 橋本, 昌宜 and Yutaka, Masuda and Takao, Onoye and Masanori, Hashimoto},
 book = {DAシンポジウム2016論文集},
 issue = {7},
 month = {Sep},
 note = {半導体製造プロセスの微細化に伴い，製造ばらつきや経年劣化による回路性能のばらつきが顕在化している．本研究は，性能ばらつきへの対策としてクリティカルパス・アイソレーションに着目する．アイソレーションは，本質的なクリティカルパス以外にスラックを与えて，遅延故障発生率を削減する．本稿では，低電圧・長寿命動作可能なアイソレーション手法を提案する．提案手法は，整数線形計画法を用いて，ゲートの故障率の総和を最大限削減し得る FF 組を選択する．アイソレーションの効果を実験で評価したところ，Vdd の 25%の削減効果を実験的に確認した．同一の動作電圧で動作させた場合，MTTF (平均故障発生時間) を 14 桁以上向上させた．面積オーバヘッドは 1.4%であった．, Device miniaturization due to technology scaling has made manufacturing variability and aging more significant, and lower supply voltage makes circuits sensitive to dynamic environmental fluctuation. These may shorten the time to failure (TTF) of fabricated chips unexpectedly. This paper focuses on critical path isolation, which increases timing slack of non-intrinsic critical paths and decreases timing error occurrence probability in the circuit, and proposes a design methodology of isolated circuits for TTF extension and/or lower voltage operation. The proposed methodology selects a set of FFs for isolation using ILP so that it maximumly reduces the sum of gate-wise failure probabilities. We evaluated MTTF (Mean Time To Failure) of circuits with/without critical path isolation and examined how much supply voltage could be reduced without MTTF degradation. Evaluation results show that circuits with the proposed critical path isolation achieved 25% supply voltage reduction with 1.4% area overhead. With the same supply voltage, MTTF was improved by 14 orders of magnitude.},
 pages = {32--37},
 publisher = {情報処理学会},
 title = {低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法},
 volume = {2016},
 year = {2016}
}