{"created":"2025-01-19T00:44:42.821941+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00174521","sets":["6164:6165:7651:8901"]},"path":["8901"],"owner":"11","recid":"174521","title":["極低電圧動作を目指したD-Nwell レス細粒度基板バイアスSRAMビットセルの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-09-07"},"_buckets":{"deposit":"15dd2d18-dfae-43f0-995a-2d15bc9e8cc0"},"_deposit":{"id":"174521","pid":{"type":"depid","value":"174521","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"極低電圧動作を目指したD-Nwell レス細粒度基板バイアスSRAMビットセルの検討","author_link":["359591","359589","359588","359587","359586","359590"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"極低電圧動作を目指したD-Nwell レス細粒度基板バイアスSRAMビットセルの検討"},{"subitem_title":"Fine-Grain Body Biasing Aware SRAM Bitcell Structure for Ultra Low Voltage Operation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"物理設計･回路設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2016-09-07","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"埼玉大学工学部"},{"subitem_text_value":"埼玉大学工学部"},{"subitem_text_value":"埼玉大学工学部"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Saitama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Saitama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Saitama University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/174521/files/IPSJ-DAS2016005.pdf","label":"IPSJ-DAS2016005.pdf"},"date":[{"dateType":"Available","dateValue":"2018-09-07"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2016005.pdf","filesize":[{"value":"895.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"35ff8bae-0de7-48a8-891f-577ec5af99a6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中馬, 良兵"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西澤, 真一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"伊藤, 和人"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryohei, Chuma","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinichi, Nishizawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuhito, Ito","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"集積回路の低消費エネルギー化のためには電源電圧の低下が有効である．しかし集積回路を構成する SRAM は論理回路よりも最低動作電圧が高い問題がある．電源電圧の低下によってトランジスタの駆動電流が低下すると，負荷となる非活性ビットセルのリーク電流によって低電圧動作が困難になる．ビットセルのリーク電流を選択的に制御する手法として，基板バイアス制御があげられる．アクセストランジスタは高い駆動電流を得るために NMOS トランジスタが利用されているが，P 型基板上の NMOS トランジスタに基板バイアスを印加するためには Deep N-Well 層が必要であり，コストが上昇する問題がある．本研究では，Deep N-Well 層を使わずに基板バイアスによるビットセルの閾値電圧の選択的制御を行うために，アクセストランジスタに PMOS を利用する SRAM ビットセルを提案する．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Lowering the supply voltage is one of a solution to achieve higher energy efficiency for VLSI circuits. Minimum operation voltage for the SRAM circuit is higher than that of the digital circuit thus it limits the minimum supply voltage for overall VLSI circuit. The minimum operation voltage for the SRAM circuit is limited by the leakage current of the access transistors inside the SRAM bitcells. Body bias technique is one of a solution to controll the leakage current of access transistors. Conventional SRAM bitcell uses NMOS transistor as an access transistor thus Deep N-Well layer is required for individual body bias. We proposes a SRAM bitcell with PMOS access trnasistor for Deep N-Well less individual body biasing and evaluate its impact on SRAM low voltage operation.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"25","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2016論文集"}],"bibliographicPageStart":"20","bibliographicIssueDates":{"bibliographicIssueDate":"2016-09-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2016"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":174521,"updated":"2025-01-20T06:39:00.263247+00:00","links":{}}