{"updated":"2025-01-20T06:58:04.960409+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00174241","sets":["581:8417:8426"]},"path":["8426"],"owner":"11","recid":"174241","title":["FPGA NIC向けノンパラメトリックオンライン外れ値検出機構"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-08-15"},"_buckets":{"deposit":"3b3cf158-59be-416e-bb5d-7f2b8cb7a9ee"},"_deposit":{"id":"174241","pid":{"type":"depid","value":"174241","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FPGA NIC向けノンパラメトリックオンライン外れ値検出機構","author_link":["356742","356741","356740","356743","356739","356738"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA NIC向けノンパラメトリックオンライン外れ値検出機構"},{"subitem_title":"A Nonparametric Online Outlier Detector for FPGA NICs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[特集：組込みシステム工学 (特選論文) ] FPGA，FPGA NIC，外れ値検出，LOF","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2016-08-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科／科学技術新興機構さきがけ／国立情報学研究所"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University / PRESTO, Japan Science and Technology Agency / National Institute of Informatics","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/174241/files/IPSJ-JNL5708002.pdf","label":"IPSJ-JNL5708002.pdf"},"date":[{"dateType":"Available","dateValue":"2018-08-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL5708002.pdf","filesize":[{"value":"12.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"7ad0a926-c244-4447-9f11-c3d8d677cafa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"林, 愛美"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"徳差, 雄太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 宏紀"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ami, Hayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuta, Tokusashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroki, Matsutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"センシング技術やInternet of Things（IoT）技術の発展にともない，生成されるセンサデータ量は増加し続け，組み込み分野においても大規模データを処理可能なセンサデータ収集システムの必要性が増している．このような膨大な量のデータの中から期待されるパターンと一致しないアイテムのみを効率的に検出するアルゴリズムとして，データセットモデルに依存しにくいノンパラメトリックな外れ値検出アルゴリズムの利用が期待されている．本論文では，ネットワークアプライアンスでの利用を想定し，10GbitEthernetインタフェースを有するFPGAネットワークインタフェースカード（FPGA NIC）上に外れ値検出機構を実現するための手法を提案する．LOF（Local Outlier Factor）は精度の高い外れ値検出アルゴリズムであるが，その計算の複雑さやデータセットモデルの大きさから，FPGAにはオフロードされていない．本論文ではLOFアルゴリズムをFPGA NICのFPGA部に実装した．正常値を含むサンプルデータパケットはFPGA NICでフィルタされ，外れ値を含むデータのみソフトウェアで処理するシステムを提案する．ただし，LOFアルゴリズムをそのままFPGA NICにオフロードすると，計算やメモリのために必要な資源が膨大な量になってしまうため，データセットモデルの一部をキャッシュするシステムを提案する．100,000サンプルを含むデータセットモデルを用いた評価の結果，45%～90%のデータがLOFによる外れ値フィルタリングNICのキャッシュにヒットし，NICによる外れ値検出を実現できた．これは，外れ値検出をすべてソフトウェアで実行した場合に比べて1.82倍～10倍の外れ値検出処理スループット向上に相当する．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"As the sensing technology and Internet of Things (IoT) technology advance, sensor data stream continuously grows in size, and thus a sensor data aggregation demands a high throughput even in embedded system domains. As outlier detection that filters non-essential data by comparing with expected patterns, especially a nonparametric outlier detection algorithm that does not depend on dataset model is an attractive choice for the sensor data aggregation. In this paper, we propose a nonparametric outlier detection mechanism using an FPGA network interface card (FPGA NIC) that equips four 10Gbit Ethernet interfaces for network appliances. We employ LOF (Local Outlier Factor) algorithm for outlier detection as it is known as a high precision algorithm. However, FPGA-based design of LOF algorithm has not been reported due to the algorithm complexity and large data set required. In our design, LOF algorithm is implemented on the FPGA and non-essential data are filtered at the NIC, while the others are processed by a software. A naive offloading of LOF algorithm to FPGA devices may significantly increase hardware resources because of complexity of the computation and its large dataset model. Thus we propose to cache only a frequently-used portion of the dataset model in the FPGA NIC. The simulation results using a dataset model containing 100,000 sample data show that 45%-90% of input data are hit to the cache and filtered at the NIC. It corresponds to a 1.82x to 10x throughput improvement on the outlier filtering compared to that of a software-based execution.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1679","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1664","bibliographicIssueDates":{"bibliographicIssueDate":"2016-08-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"57"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:44:27.773610+00:00","id":174241,"links":{}}