{"created":"2025-01-19T00:43:16.995486+00:00","updated":"2025-01-20T07:33:22.325662+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00172937","sets":["1164:1579:8444:8870"]},"path":["8870"],"owner":"11","recid":"172937","title":["Zynqを用いた衛星エンジンシミュレーションの高速化の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-08-01"},"_buckets":{"deposit":"65f921c2-168d-4085-bc67-6aa992f3cb28"},"_deposit":{"id":"172937","pid":{"type":"depid","value":"172937","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Zynqを用いた衛星エンジンシミュレーションの高速化の検討","author_link":["352295","352293","352298","352296","352301","352297","352294","352299","352292","352300"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Zynqを用いた衛星エンジンシミュレーションの高速化の検討"},{"subitem_title":"Acceleration of the satellite engine simulation using Zynq","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA・シミュレーション","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"宇宙航空研究開発航空技術部門数値解析技術研究ユニット"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"宇宙航空研究開発航空技術部門数値解析技術研究ユニット"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Numerical Simulation Research Unit, Aeronautical Technology Directorate, Japan Aerospace Exploration Agency","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Numerical Simulation Research Unit, Aeronautical Technology Directorate, Japan Aerospace Exploration Agency","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/172937/files/IPSJ-ARC16221041.pdf","label":"IPSJ-ARC16221041.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC16221041.pdf","filesize":[{"value":"444.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"6ff06f0e-1114-4745-bd49-4301f3878e23","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"酒井, 諒太郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"宮島, 敬明"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"杉本, 成"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤田, 直行"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryotaro, Sakai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takaaki, Miyajima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naru, Sugimoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoyuki, Fujita","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"衛星に搭載されるホールスラスタは，ホール効果を利用した電気推進エンジンのひとつであり，他の電気推進エンジンよりも電力の推進エネルギーへの変換効率が高いため，近年盛んに研究が行われている．Full-PIC(Particle-In-Cell) 法は，ホールスラスタの高精度なシミュレーション手法であるが，非常に計算コストが高い．さらに，コードの構造上 GPU による高速化は適さず，FPGA を用いた高速化が検討されている．本研究では，ホールスラスタのシミュレーションの新たな実行環境として，省電力で低コストな CPU-FPGA 密結合アーキテクチャである Zynq を採用した．また，Zynq の衛星への組み込みを検討した．そして，高負荷なフェーズの処理を Zynq 上の FPGA にオフロードすることにより高速化を行った．実装には Xilinx Zed Board を採用し，高位合成ツールである Vivado HLS を用いて効率化を図った．FPGA にオフロードした高負荷な処理は，ARMCortex-A9 667MHz と比較して最大 14.95 倍の高速化を達成した．また，フェーズ全体では 5.17 倍の高速化の達成が見込めた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"41","bibliographicVolumeNumber":"2016-ARC-221"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":172937,"links":{}}