{"created":"2025-01-19T00:43:16.132720+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00172921","sets":["1164:1579:8444:8870"]},"path":["8870"],"owner":"11","recid":"172921","title":["FPGAを用いたFat TreeベースNoCの高速エミュレーション"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-08-01"},"_buckets":{"deposit":"7171097c-3a9d-41dd-81bd-55fe51475092"},"_deposit":{"id":"172921","pid":{"type":"depid","value":"172921","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FPGAを用いたFat TreeベースNoCの高速エミュレーション","author_link":["352185","352182","352183","352184"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAを用いたFat TreeベースNoCの高速エミュレーション"},{"subitem_title":"A Fast Emulation System for Fat-Tree-Based Network-on-Chips","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ネットワーク性能","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学情報理工学院"},{"subitem_text_value":"東京工業大学情報理工学院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Computing, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"School of Computing, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/172921/files/IPSJ-ARC16221025.pdf","label":"IPSJ-ARC16221025.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC16221025.pdf","filesize":[{"value":"639.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"9deefdd2-5702-4d29-99a6-f7521cd4433c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"ThiemVan, Chu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉瀬, 謙二"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Thiem, Van Chu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kenji, Kise","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Network-on-Chip(NoC) は， メニーコアプロセッサのチップ内インターコネクションネットワークとして用いられるようになった．新たな NoC を研究開発するには，正確かつ高速なシミュレーション環境が必要となる．しかし，従来のソフトウェアシミュレータは，数百から数千個のノードから構成される NoC のようにシミュレーション規模が大きい場合，速度が非常に遅くなり，現実的な時間でシミュレーションを行うことが困難である．そのため，最近では，FPGA ベースの高速 NoC エミュレータが注目されている．既存 FPGA ベース NoC エミュレータのほとんどは，1,000 ノード以下の 2 次元メッシュ NoC しかサポートしておらず，比較的単純な NoC モデルを採用しているが，従来のソフトウェアシミュレータよりも数百倍までの速度向上を達成している．本稿では，単一の FPGA を用いて最大数千ノードまでの fat tree ベース NoC の挙動を，サイクルレベルで高速にエミュレーションするための手法を提案する．評価では，4,096 コア及び 6,144 ルータから構成される fat tree ベース NoC を単一の Virtex-7FPGA でエミュレーションできることを示す．提案システムは，NoC 研究で広く使われているソフトウェアシミュレータ BookSim と比較して，精度を維持したまま，232 倍高速である．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2016-ARC-221"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":172921,"updated":"2025-01-20T07:32:55.706604+00:00","links":{}}