{"created":"2025-01-19T00:43:15.225998+00:00","updated":"2025-01-20T07:32:26.218705+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00172904","sets":["1164:1579:8444:8870"]},"path":["8870"],"owner":"11","recid":"172904","title":["プロセッサコアへの小規模ハードウェアトランザクショナルメモリ実装手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-08-01"},"_buckets":{"deposit":"975c9891-c31b-461b-aa06-0111103bcf8e"},"_deposit":{"id":"172904","pid":{"type":"depid","value":"172904","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"プロセッサコアへの小規模ハードウェアトランザクショナルメモリ実装手法","author_link":["352105","352110","352106","352107","352109","352112","352108","352111"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"プロセッサコアへの小規模ハードウェアトランザクショナルメモリ実装手法"},{"subitem_title":"Efficient implementation method of a compact HTM into processor cores","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"トランザクショナルメモリ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三重大学大学院工学研究"},{"subitem_text_value":"三重大学大学院工学研究"},{"subitem_text_value":"三重大学大学院工学研究"},{"subitem_text_value":"三重大学大学院工学研究"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Engineering, Mie University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Engineering, Mie University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Engineering, Mie University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Engineering, Mie University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/172904/files/IPSJ-ARC16221008.pdf","label":"IPSJ-ARC16221008.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC16221008.pdf","filesize":[{"value":"438.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"dc591baf-8f70-4fa2-af14-c799e1accb18","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"櫻田, 賢大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐々木, 敬泰"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"深澤, 祐樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"近藤, 利夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takahiro, Sakurada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahiro, Sasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuki, Fukazawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshio, Kondo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現在，共有メモリ型マルチコアプロセッサが広く普及しており，並列処理に利用されている．並列処理において，一般に並列プログラムの実行順序が非決定的であることから，共有メモリは並行する複数のプロセスが実行順序に依存しないデータの一貫性を保持する必要がある．多くのプロセッサでは， このような排他制御手法として，アクセス権により制御するロックが採用されている． しかし， ロックでは並列処理を実質的に逐次処理で行うため，効率的ではない．そこで，並列に処理を行うために投機的なアクセスを許すトランザクショナルメモリと呼ばれる手法が提案されている．特にハードウェアにより実現したトランザクショナルメモリは，いくつかの商用プロセッサにおいても採用されている． しかし，それらのプロセッサでは， トランザクション処理を担うハードウェアの規模が大きい問題がある．そこで，扱うトランザクションを限定的にし， トランザクショナルメモリをコア内で留める，組込み用プロセッサ等の小規模なシステム向けのハードウェアトランザクショナルメモリの実装手法を提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Shared-memory multi-core processors have been widely used. Because execution order of parallel program is non-deterministic, system should maintain the data consistency without depending on execution order. Transactional memory (TM) is proposed as an exclusive control method required for parallel processing that replaces the lock. In this study, we propse implementation methodology of hardware TM to expand the store buffer in the processor core for embedded systems.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"2016-ARC-221"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":172904,"links":{}}