{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00172903","sets":["1164:1579:8444:8870"]},"path":["8870"],"owner":"11","recid":"172903","title":["トランザクショナルメモリにおける実行パスを考慮したスケジューリング手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-08-01"},"_buckets":{"deposit":"369965e2-883d-4766-8a49-ed822231e522"},"_deposit":{"id":"172903","pid":{"type":"depid","value":"172903","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"トランザクショナルメモリにおける実行パスを考慮したスケジューリング手法","author_link":["352101","352103","352102","352104"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"トランザクショナルメモリにおける実行パスを考慮したスケジューリング手法"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"トランザクショナルメモリ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/172903/files/IPSJ-ARC16221007.pdf","label":"IPSJ-ARC16221007.pdf"},"date":[{"dateType":"Available","dateValue":"2018-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC16221007.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"cd8ad364-2549-48b4-acb2-626c515cc79d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"廣田, 杏珠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田渕, 茉也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"間下, 恵介"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチコア環境では，一般的にロックを用いて共有リソースへのメモリアクセスを調停する．しかし，ロックにはデッドロックの発生や並列度の低下などの問題があるため，ロックを使用しない並行性制御機構としてトランザクショナルメモリ （TM） が提案されている．この機構をハードウェア上で実現したハードウェアトランザクショナルメモリ （HTM） では，共有リソースへのメモリアクセスが競合しない限りトランザクションが投機的に実行される．この HTM ではトランザクションの実行が投機的であるため，競合が発生し性能が低下する可能性がある．この問題に対し，スケジューリングの改良により競合を抑制する研究が数多く行われてきた．しかし従来の手法はいずれも，分岐命令などに起因するトランザクション内の実行パスの変化について考慮していない．そこで本稿では，トランザクション開始時に実行パスを予測して実行時間を見積もり，それに基づいて競合を回避するスケジューリング手法を提案する．シミュレーションによる評価の結果，16 スレッドで最大 61.6%，平均 13.8%の実行サイクル数削減を確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2016-ARC-221"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:43:15.173497+00:00","updated":"2025-01-20T07:32:24.613471+00:00","id":172903}