{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00016680","sets":["934:935:959:961"]},"path":["961"],"owner":"1","recid":"16680","title":["X86アーキテクチャのメモリ階層を考慮した最適なRegister Allocation"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-07-15"},"_buckets":{"deposit":"15a59db0-229f-49d0-b087-8699d2ffe40d"},"_deposit":{"id":"16680","pid":{"type":"depid","value":"16680","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"X86アーキテクチャのメモリ階層を考慮した最適なRegister Allocation","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"X86アーキテクチャのメモリ階層を考慮した最適なRegister Allocation"},{"subitem_title":"An Optimal Register Allocation for X86 Architecture with Consideration of Memory Hierarchy","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"発表概要","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2004-07-15","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学基盤情報学専攻"},{"subitem_text_value":"東京大学情報基盤センター"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Frontier Informatics, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Center, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/16680/files/IPSJ-TPRO4509011.pdf"},"date":[{"dateType":"Available","dateValue":"2006-07-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TPRO4509011.pdf","filesize":[{"value":"34.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6823ae58-772d-4c15-b5af-0da57d679c04","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"堀本, 和秀"},{"creatorName":"佐藤周行"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazuhide, Horimoto","creatorNameLang":"en"},{"creatorName":"Hiroyuki, Sato","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11464814","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7802","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"コンピュータでは，高い性能を実現するためにキャッシュを上手く利用することが有効である．そのため近年のプロセッサは一般的にある程度のメモリ階層を持っており，コンパイラは高い性能を実現するためにこのメモリ階層を考慮する必要がある．X86のようなアーキテクチャでは，レジスタの数が少ないことや，命令のオペランドをメモリにできることからRegister Allocationは難しくなる．Graph Coloringのような従来のヒューリスティックな方法ではその難しくなったRegister Allocationで良い性能を出せる解を求められるかは自明ではない．本研究の目的は，0-1 Integer Programmingを用いてキャッシュを有効利用できるRegister Allocationの最適解を求めるためのモデル化を行い，既存のコンパイラとの比較と評価を行うことである．本発表では，Pentium 4のアーキテクチャのRegister/Cache/Memoryの階層を考慮したRegister Allocationを行うための性能モデルの0-1 Integer Programmingによる定式化を行い，その実装と性能の測定を行った．さらに既存のコンパイラとの比較と評価を試み，従来のヒューリスティックスの改善点などについて考察を行った．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In modern proceccors, memory hierarchy must be utilized effectively for achieving high performance. Compilers must be designed to exploit the memory hierarchy. For the X86 architecture that has few registers, and furthermore has possible memory operands, register allocation is never trivial. In other words, it is not clear if conventional heuristics such as graph coloring can give the best register allocation. Our goal is to formulate register allocation for Pentium 4 with 0-1 Integer Programming. This scheme is proved to be optimum for the performance model which considers the register/cache/memory hierarchy. In this presentation, we show the scheme of generaing 0-1 Integer Programming for a given code, and apply the solutions for register allocation. Furthermore, we evaluate the solutions on realistic platform.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"84","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌プログラミング（PRO）"}],"bibliographicPageStart":"84","bibliographicIssueDates":{"bibliographicIssueDate":"2004-07-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"SIG09(PRO22)","bibliographicVolumeNumber":"45"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":16680,"updated":"2025-01-22T23:44:42.489848+00:00","links":{},"created":"2025-01-18T22:49:53.102972+00:00"}