{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00015948","sets":["581:892:896"]},"path":["896"],"owner":"1","recid":"15948","title":["マルチプロセッサシステムにおける主記憶最適配分問題の解析"],"pubdate":{"attribute_name":"公開日","attribute_value":"1984-05-15"},"_buckets":{"deposit":"f8a0dbf8-ef1d-4468-8435-5fa6eb326359"},"_deposit":{"id":"15948","pid":{"type":"depid","value":"15948","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチプロセッサシステムにおける主記憶最適配分問題の解析","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチプロセッサシステムにおける主記憶最適配分問題の解析"},{"subitem_title":"Analysis of Memory Fartitioning for Multiprogramming - Multiprocessor Computer Systems","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1984-05-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東北大学大型計算機センター"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Computer Center, Tohoku University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/15948/files/IPSJ-JNL2503014.pdf"},"date":[{"dateType":"Available","dateValue":"1986-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL2503014.pdf","filesize":[{"value":"535.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5f3045ca-4cbb-4156-b6d3-116eebb1123b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1984 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"坂田, 真人"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masato, Sakata","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"最近の大型計算機システムは仮想記憶を採用し マルチ・プロセッサ構成とすることが多い.普通 多重プログラミングの実行環境のもとで複数個のバッチジョブとTSSジョブがCPU 主記憶などのシステムリソースを共用する形態で処理され システムのスループットやTSSのレスポンスはこの仮想記憶の制御方式に著しい影響を受ける.すなわち 主記憶を処理中のプログラムにどのように配分するのが最適かという問題が提起される.本論文では 主記憶割当て方式の単純な一方式である固定割当て法について マルチ・プロセッサ環境下で検討するため 計算機システムをBCMP型の閉じた待ち行列網にモデル化して議論している.従来 シングル・プロセッサ・モデルでは 主記憶をおのおののプログラムに均等に配分するかあるいは極端に偏って配分するかのいずれかの方策を採れば 最適となることが明らかになっていた.本論文ではこの結果がマルチ・プロセッサ環境ならびにより一般化したライフタイム関数の場合にも成立することを示した.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"457","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"451","bibliographicIssueDates":{"bibliographicIssueDate":"1984-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"25"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"updated":"2025-01-23T00:05:57.292913+00:00","created":"2025-01-18T22:49:21.396360+00:00","id":15948}