{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00159093","sets":["1164:2036:8446:8684"]},"path":["8684"],"owner":"11","recid":"159093","title":["FPGA向けMBU訂正回路の提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-05-04"},"_buckets":{"deposit":"556c4be3-2955-4952-a705-45403ad6ef9a"},"_deposit":{"id":"159093","pid":{"type":"depid","value":"159093","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FPGA向けMBU訂正回路の提案","author_link":["305598","305600","305603","305602","305593","305592","305599","305596","305594","305601","305595","305597"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA向けMBU訂正回路の提案"},{"subitem_title":"Multi bit soft error tolerant FPGA architecture","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"検証・信頼性","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-05-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/159093/files/IPSJ-SLDM16176007.pdf","label":"IPSJ-SLDM16176007.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM16176007.pdf","filesize":[{"value":"1.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"e5be13a6-70af-40c9-9d39-635d6737f477","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中村, 祐士"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"寺岡, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"尼崎, 太樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"久我, 守弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"末吉, 敏則"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuji, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Teraoka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Motoki, Amagasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Morihiro, Kuga","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Sueyoshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"トランジスタサイズの微細化により，メモリに対するソフトエラーの影響が顕著になってきている．微細化がナノスケールに達した現在，一度の放射線衝突により複数のビットが反転する MBU(Multiple Bit Upset) が問題となっている．既存の対策手法として TMR(Triple Modular Redundancy) や ECC(Error Correcting Code) が挙げられるが，大きな面積を必要とするうえ，MBU に対して脆弱である．そこで本研究では，FPGA のコンフィギュレーションメモリを対象とした DMR(Double Modular Redundancy) ベースエラー訂正回路を提案する．さらに，この提案回路とビットインターリーブ法を組み合わせることで，MBU への対策を行う．この際，メモリに応じたビットインターリーブ距離を算出するために，MBU パターンとその確率を出力するソフトエラーシミュレータの開発を行う．評価より，DMR ベースエラー訂正回路は ECC や TMR と比べて面積を削減することができることを確認した．また，シミュレーションを行った結果，提案の回路構成で最適なピットインターリーブ距離は 4 であることが分かった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a MBU (Multiple Bit Upset). Traditional fault tolerance technologies such as TMR (Triple Modular Redundancy) and ECC (Error Correcting Code) occupy the large area and have vulnerability to MBU. In this research, we propose DMR (Double Modular Redundancy) based error correct circuit and employ a combination of proposed circuit and the interleaving technique to mitigate MBU. In addition, we explain soft error simulator developed to calculate bit interleaving distance. The results show that the area of proposed circuit is the smallest when we compare the proposed circuit, ECC based error correct circuit and TMR. Simulation results show that the interleaving distance which can conceal all MBU patterns is 4.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-05-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2016-SLDM-176"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":159093,"updated":"2025-01-20T12:48:15.551311+00:00","links":{},"created":"2025-01-19T00:32:14.236110+00:00"}