Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler

• Item type: Journal(1)
• 公開日: 2016-04-15
• タイトル: Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler
• タイトル / 言語: en
• タイトル: Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [一般論文] low-power consumption, automatic parallelizing compiler, multi-core processor, Android
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者名: Bui, Duc,Binh; Tomohiro, Hirano; Hiroki, Mikami; Hideo, Yamamoto; Keiji, Kimura; Hironori, Kasahara
• 著者名(英): Bui, Duc Binh; Tomohiro, Hirano; Hiroki, Mikami; Hideo, Yamamoto; Keiji, Kimura; Hironori, Kasahara
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: The emergence of multi-core processors in smart devices promises higher performance and low power consumption. The parallelization of applications enables us to improve their performance. However, simultaneously utilizing many cores would drastically drain the device battery life. This paper shows a demonstration system of real-time video processing combined with power reduction controlled by the OSCAR automatic parallelization compiler on ODROID-X2, an open Android development platform based on Samsung Exynos4412 Prime with 4 ARM Cortext-A9 cores. In this paper, we exploited the DVFS framework, core partitioning, and profiling technique and OSCAR parallelization - power control algorithm to reduce the total consumption in a real-time video application. The demonstration results show that it can cut power consumption by 42.8% for MPEG-2 Decoder application and 59.8% for Optical Flow application by using 3 cores in both applications.; \n------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.24(2016) No.3 (online); ------------------------------
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: The emergence of multi-core processors in smart devices promises higher performance and low power consumption. The parallelization of applications enables us to improve their performance. However, simultaneously utilizing many cores would drastically drain the device battery life. This paper shows a demonstration system of real-time video processing combined with power reduction controlled by the OSCAR automatic parallelization compiler on ODROID-X2, an open Android development platform based on Samsung Exynos4412 Prime with 4 ARM Cortext-A9 cores. In this paper, we exploited the DVFS framework, core partitioning, and profiling technique and OSCAR parallelization - power control algorithm to reduce the total consumption in a real-time video application. The demonstration results show that it can cut power consumption by 42.8% for MPEG-2 Decoder application and 59.8% for Optical Flow application by using 3 cores in both applications.; \n------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.24(2016) No.3 (online); ------------------------------
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 57, 号 4, 発行日 2016-04-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764