@techreport{oai:ipsj.ixsq.nii.ac.jp:00158337,
 author = {Masato, Yoshimi and Yasin, Oge and Celimuge, Wu and Tsutomu, Yoshinaga and Masato, Yoshimi and Yasin, Oge and Celimuge, Wu and Tsutomu, Yoshinaga},
 issue = {43},
 month = {Mar},
 note = {This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency {e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput., This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency {e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput.},
 title = {Design and Evaluation of Low-Latency Handshake Join on FPGA},
 year = {2016}
}