Design and Evaluation of Low-Latency Handshake Join on FPGA

• Item type: SIG Technical Reports(1)
• 公開日: 2016-03-17
• タイトル: Design and Evaluation of Low-Latency Handshake Join on FPGA
• タイトル / 言語: en
• タイトル: Design and Evaluation of Low-Latency Handshake Join on FPGA
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: FPGA・ディペンダビリティ
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属: Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属: Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属: Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatioii Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatioii Systems, University of Electro-Communications
• 著者名: Masato, Yoshimi; Yasin, Oge; Celimuge, Wu; Tsutomu, Yoshinaga
• 著者名(英): Masato, Yoshimi; Yasin, Oge; Celimuge, Wu; Tsutomu, Yoshinaga
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency {e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency {e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12149313
• 書誌情報: 研究報告組込みシステム（EMB）; 巻 2016-EMB-40, 号 43, p. 1-6, 発行日 2016-03-17
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-868X
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会