{"created":"2025-01-18T22:48:45.425513+00:00","updated":"2025-01-23T00:29:53.638273+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00015121","sets":["581:833:834"]},"path":["834"],"owner":"1","recid":"15121","title":["並列推論マシンPIM/pのアーキテクチャ"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-12-15"},"_buckets":{"deposit":"e2052125-d44c-4e5e-80a6-6da325744674"},"_deposit":{"id":"15121","pid":{"type":"depid","value":"15121","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"並列推論マシンPIM/pのアーキテクチャ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"並列推論マシンPIM/pのアーキテクチャ"},{"subitem_title":"The Architecture of Parallel Inference Machine PIM/p","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：並列処理","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1989-12-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"（株）富士通研究所人工知能研究部"},{"subitem_text_value":"（株）富士通研究所人工知能研究部"},{"subitem_text_value":"（株）富士通研究所人工知能研究部"},{"subitem_text_value":"（財）新世代コンピュータ技術開発機構第4研究室"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Artificial Intelligence Laboratory, FUJITSU LABORATORIES LTD","subitem_text_language":"en"},{"subitem_text_value":"Artificial Intelligence Laboratory, FUJITSU LABORATORIES LTD","subitem_text_language":"en"},{"subitem_text_value":"Artificial Intelligence Laboratory, FUJITSU LABORATORIES LTD","subitem_text_language":"en"},{"subitem_text_value":"Fourth Research Laboratory, Institute for New Generation Computer Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/15121/files/IPSJ-JNL3012008.pdf"},"date":[{"dateType":"Available","dateValue":"1991-12-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3012008.pdf","filesize":[{"value":"729.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"771369fe-01d1-48b1-9f1b-173a8bd4ec79","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1989 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"服部, 彰"},{"creatorName":"篠木, 剛"},{"creatorName":"久門, 耕一"},{"creatorName":"後藤厚宏"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Hattori","creatorNameLang":"en"},{"creatorName":"Tsuyoshi, Shinogi","creatorNameLang":"en"},{"creatorName":"Kouichi, Kumon","creatorNameLang":"en"},{"creatorName":"Atsuhiro, Goto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本マシンは並列論理型言語KL1で記述された知識処理プログラムの高速処理を目的とする数百台規模のマルチプロセッサであり 第五世代コンピュータプロジェクトの中で開発中である.KL1言語で多用されるプロセス間の通信・同期を高速処理するため 10台程度のプロセッサ(PE)をメモリ共有バス結合したクラスタをネットワークにより結合する二階層構成を採った.本論文では特に クラスタとネットワークで採用した高速化アーキテクチャの主な特徴と評価について述べる.PE台数に比例したクラスタ性能を実現するためには 共有バスの通信量を減らすことが重要である.共有パス上の命令コード量とオペランドデータ量を減らすために 命令を動的に高機能化するマクロ命令呼び出し機構とキャッシュメモリの動作をソフトから制御する命令をそれぞれ設計した.これらの機構や命令がバスの通信量の低減とクラスタ性能の向上に有効なことをシミュレーションにより確認した.次に クラスタ間のハイパキューブネットワークの各ルータノ-ドに複数PEを接続することにより ネットワーク性能を有効利用できることをシミュレーションにより確認し 採用した.また クラスタ間ネットワークのデッドロックフリーなルーティング法として固定ルーティング法でも十分なスループットが得られることを確認し 採用した.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1592","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1584","bibliographicIssueDates":{"bibliographicIssueDate":"1989-12-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicVolumeNumber":"30"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"ハードウェア"}]},"weko_creator_id":"1"},"id":15121,"links":{}}