{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00147504","sets":["1164:1579:8444:8445"]},"path":["8445"],"owner":"11","recid":"147504","title":["ビルディングキューブ法に基づくステンシル計算の高位合成ベースFPGA実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-01-12"},"_buckets":{"deposit":"73ba38fd-a512-4a93-9fc2-b963f8578faf"},"_deposit":{"id":"147504","pid":{"type":"depid","value":"147504","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ビルディングキューブ法に基づくステンシル計算の高位合成ベースFPGA実装","author_link":["234856","234858","234860","234854","234859","234855","234853","234857"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ビルディングキューブ法に基づくステンシル計算の高位合成ベースFPGA実装"},{"subitem_title":"Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"数値計算","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-01-12","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"長崎大学大学院工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/147504/files/IPSJ-ARC16218022.pdf","label":"IPSJ-ARC16218022.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC16218022.pdf","filesize":[{"value":"808.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"12932499-6470-4e72-9d86-e124dd665da1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"副島, 梨恵"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"翁, 浩ニ"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柴田, 裕一郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小栗, 清"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Rie, Soejima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koji, Okina","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuichiro, Shibata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kiyoshi, Oguri","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"解適合格子法の一種であるビルディングキューブ法 (BCM) は計算領域を異なる大きさの直交格子に分割するが，各格子のデータサイズ・演算フローは均一化されており，並列計算との親和性が高い．本稿では，BCM 法によるステンシル計算を FPGA 上に容易に実装可能なフレームワークを高位合成系上にクラスライブラリとして作成した．熱拡散シミュレーションをベンチマークとして，演算性能，メモリアクセス性能及び回路規模を評価し，異なる大きさの格子間のデータ授受機構のオーバーヘッドを明らかにした．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In building-cube method (BCM), which is one of the adaptive mesh refinement, the computational region is divided into a number of sub-domains with various sizes. One of advantages of the BCM that it suits parallel processing, due to each sub-domain has a similar data size and a similar computing flow in spite of the difference in size. This paper presents implementation of a class library framework on a high-level synthesis system, which aims at enabling easy FPGA implementation of BCM-based stencil computation. The proposed framework is evaluated with a heat conduction simulation as a benchmark application in terms of computing performance, memory performance and hardware amount, so that overheads of a mechanism of data exchange between sub-domains with different size are revealed.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-01-12","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22","bibliographicVolumeNumber":"2016-ARC-218"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":147504,"updated":"2025-01-20T12:55:20.720920+00:00","links":{},"created":"2025-01-19T00:22:36.585661+00:00"}