{"id":147028,"updated":"2025-01-20T17:43:59.475175+00:00","links":{},"created":"2025-01-19T00:22:18.251621+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00147028","sets":["1164:2036:8446:8447"]},"path":["8447"],"owner":"11","recid":"147028","title":["H-Treeトポロジを用いたFPGA配線構造の一検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2016-01-12"},"_buckets":{"deposit":"928af55b-9491-42ef-b559-6e2d3887ef94"},"_deposit":{"id":"147028","pid":{"type":"depid","value":"147028","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"H-Treeトポロジを用いたFPGA配線構造の一検討","author_link":["232049","232044","232036","232042","232041","232037","232043","232046","232040","232048","232038","232047","232039","232045"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"H-Treeトポロジを用いたFPGA配線構造の一検討"},{"subitem_title":"FPGA routing structure based on H-Tree topology","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGAアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2016-01-12","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"},{"subitem_text_value":"熊本大学大学院自然科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/147028/files/IPSJ-SLDM16174002.pdf","label":"IPSJ-SLDM16174002.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM16174002.pdf","filesize":[{"value":"582.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"54448e43-3913-4c24-a0a4-16f2f3ae01bf","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2016 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"石井, 友樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"池邊, 雅登"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"趙, 謙"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"尼崎, 太樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"久我, 守弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"末吉, 敏則"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuki, Ishii","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masato, Ikebe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Qian, Zhao","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Motoki, Amagasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Morihiro, Kuga","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Sueyoshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA(Field Programmable Gate Array) は柔軟性実現のために多くの配線を備えており，配線部が性能に与える影響は大きい特に近年は大規模化に伴い配線混雑の問題が深刻になってきている．配線混雑が起きることで配線の競合が起こり配線迂回が生じる．配線迂回は更なる配線混雑を引き起こすことや，遅延，面積に大きく影響している．配線混雑の原因としてネットリスト中のごく一部のファンアウトの多い論理クラスタが影響していることがわかっている．本研究では配線混雑の原因であるファンアウトの多い論理クラスタに着目し，ファンアウトの多い論理クラスタ専用に H-Tree トポロジを用いることを検討するために H-Tree が面積に与える影響に関して調査を行った．その結果，H-Tree に要する面積は非常に小さく H-Tree 配線によりホモジニアス構造のトラック数を削減することができれば，H-Tree 配線を持つホモジニアス構造は非常に有効であることがわかった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resources have large impact to the peformance of FPGA. The routing congestion causes competitive of signals and routing detours which degrade the peformance of FPGA. We have been found that the effect is small portion of the high fanout nets as the cause of wiring congestion, delay in the removal of them, it has also been reported that the area can be reduced. This is a study focusing on the high fanouts net is the cause of the wiring congestion, consider the FPGA routing structure of the high fanouts net based on H-Tree topology. As a result, if it is possible to reduce the number of tracks of the homogeneous structure by the H-Tree, homogeneous structure with a H-Tree wiring was found to be very effective.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2016-01-12","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"2016-SLDM-174"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}