{"id":146161,"updated":"2025-01-20T18:05:28.079115+00:00","links":{},"created":"2025-01-19T00:21:39.484796+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00146161","sets":["1164:2036:7856:8381"]},"path":["8381"],"owner":"11","recid":"146161","title":["タイミングエラー予測回路によるデータ依存最適化回路設計とそのFPGA評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-11-24"},"_buckets":{"deposit":"3badec22-55c1-4f7a-934c-7792c27547f5"},"_deposit":{"id":"146161","pid":{"type":"depid","value":"146161","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"タイミングエラー予測回路によるデータ依存最適化回路設計とそのFPGA評価","author_link":["227191","227188","227186","227189","227187","227190"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"タイミングエラー予測回路によるデータ依存最適化回路設計とそのFPGA評価"},{"subitem_title":"A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"予測と測定","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工学専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科電子光システム学専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic and Photonic Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/146161/files/IPSJ-SLDM15173035.pdf","label":"IPSJ-SLDM15173035.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM15173035.pdf","filesize":[{"value":"439.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"3319c728-8fb7-413b-b42e-46065c9197a3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazushi, Kawamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"LSI 内部のパス遅延及び遷移確率は入力データに応じて様々に変動する．この性質を利用することで計算精度をわずかに落としながらも高速に動作する LSI の設計が可能になる．入力データにもとづき対象回路中で最適化すべきコーンを特定するため，提案アルゴリズムは仮想的にクロック周期を変化させ，タイミングエラー予測回路により対象回路の動作をシミュレーションする．このシミュレーションは高速に実行可能であり，適用範囲が広い特長を持つ．本稿では ISCAS85 ベンチマークを対象に FPGA 上で回路動作シミュレーションし，商用設計ツールを用いてコーン最適化を実行した結果を報告する．評価実験において，2.1％以下の計算誤差を許容する制約のもと提案アルゴリズムにより最適化された回路は，誤差を許容しない場合と比べて最大 16.7％高速化することに成功した．本実験の結果は，提案アルゴリズムによる高速化の効果が入力データに応じて変化することも示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, and this property can be exploited to design high-performance approximation circuit with a negligible error rate. In order to identify cones to be optimized based on input data, for a target circuit, our proposed algorithm virtually varies the operating clock frequency and simulates its behavior by incorporating timing error prediction circuits into it. This simulation can be run at a fast speed and applied in a wide range of situations. For the implementation and evaluation of our algorithm, we construct a novel design flow which identifies cones to be optimized on FPGA and then optimizes them by using a commercially available design tool. In this paper, our algorithm is applied to ISCAS85 benchmarks. Experimental results show that our algorithm can achieve performance increase by up to 16.7% within acceptable error rate of 2.1% compared with conventional design techniques. These results also show that the efficiency of our algorithm varies depending on input data.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"35","bibliographicVolumeNumber":"2015-SLDM-173"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}