{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00146147","sets":["1164:2036:7856:8381"]},"path":["8381"],"owner":"11","recid":"146147","title":["配線遅延とクロックスキューを利用したフロアプラン指向FPGA高位合成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-11-24"},"_buckets":{"deposit":"f61d30d2-7a00-4f7e-8a8f-554bf4cd32f6"},"_deposit":{"id":"146147","pid":{"type":"depid","value":"146147","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"配線遅延とクロックスキューを利用したフロアプラン指向FPGA高位合成手法","author_link":["227064","227069","227068","227062","227067","227066","227063","227065"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"配線遅延とクロックスキューを利用したフロアプラン指向FPGA高位合成手法"},{"subitem_title":"A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"配置配線","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Grad. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/146147/files/IPSJ-SLDM15173021.pdf","label":"IPSJ-SLDM15173021.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM15173021.pdf","filesize":[{"value":"424.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"6cb796e5-192b-455a-a994-6ccce9b6f492","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"藤原, 晃一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Koichi, Fujiwara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazushi, Kawamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA では近年プロセスの微細化が進み，配線遅延とクロックスキューが回路の動作周波数を著しく悪くする恐れがある．従って，近年注目されている FPGA 向けフロアプラン指向高位合成では高位合成段階で配線遅延とクロックスキューを考慮することが小遅延な回路を設計するために重要である．本稿では，FPGA の配線遅延とクロックスキューを考慮しクリティカルパスを最適化するフロアプラン指向高位合成手法を提案する．提案手法は，レジスタ分散型アーキテクチャの 1 つである HDR アーキテクチャを用いて，高位合成段階でモジュールの配置を行う．フロアプラン情報より高位合成段階で FPGA でのモジュール間の配線遅延とクロックスキューを見積もる．さらに，これらを含めて各パスの遅延を見積もり，クリティカルパスを特定する．データパスを形成するスケジューリング/FU バインデイングとモジュール配置を決定するフロアプランにおいてクリティカルパスの最適化を図りレイテンシーの向上を目指す．提案手法は，従来手法に比べてレイテンシーを最大 24％削減した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a circuit and then may degrade operation frequency. We must consider interconnection delays and clock skews in floorplan-aware FPGA-HLS flow to design circuits having small latency. In this paper, we propose a floorplan-aware high-level synthesis algorithm for FPGA designs optimizing operation frequency of a circuit by improving interconnection delays and clock skews on the critical-path. Our target architecture is HDR, one of distributed-register architectures, and then we can consider module floorplan easily. Based on it, we estimate the delay of each signal path including interconnection delays and clock-skews, and identify the critical-path. To optimize them, we propose a novel scheduling/FU binding method and a novel floorplanning method. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 24% compared with conventional approaches.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"21","bibliographicVolumeNumber":"2015-SLDM-173"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":146147,"updated":"2025-01-20T18:05:04.808446+00:00","links":{},"created":"2025-01-19T00:21:38.759727+00:00"}