{"id":145535,"updated":"2025-01-20T18:18:43.597457+00:00","links":{},"created":"2025-01-19T00:21:09.682185+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00145535","sets":["1164:2036:7856:8349"]},"path":["8349"],"owner":"11","recid":"145535","title":["三次元積層型浮動小数点積和演算器の回路分割手法の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-10-19"},"_buckets":{"deposit":"26d7aa30-cbbc-48aa-9a49-2ebea3f09c6c"},"_deposit":{"id":"145535","pid":{"type":"depid","value":"145535","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"三次元積層型浮動小数点積和演算器の回路分割手法の検討","author_link":["224699","224705","224706","224701","224702","224703","224704","224700"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"三次元積層型浮動小数点積和演算器の回路分割手法の検討"},{"subitem_title":"Design of a 3-D Stacked Floating-point Fused Multiply-Add Unit","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2015-10-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"山形大学大学院理工学研究科情報科学専攻"},{"subitem_text_value":"山形大学大学院理工学研究科情報科学専攻"},{"subitem_text_value":"東北大学サイバーサイエンスセンター"},{"subitem_text_value":"東北大学サイバーサイエンスセンター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Yamagata University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Yamagata University","subitem_text_language":"en"},{"subitem_text_value":"Cyberscience Center, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Cyberscience Center, Tohoku University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/145535/files/IPSJ-SLDM15172005.pdf","label":"IPSJ-SLDM15172005.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM15172005.pdf","filesize":[{"value":"978.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"b26c129d-804d-48a6-a1cf-789282b6fa08","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"細川, 磨生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"多田, 十兵衛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"江川, 隆輔"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小林, 広明"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Maiki, Hosokawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Jubee, Tada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryusuke, Egawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，LSI の更なる性能向上の手段として 3 次元積層技術が注目されている．三次元積層技術を用いて浮動小数点演算器を実装する場合，回路分割手法により性能が大きく変化する．本研究では，三次元積層型浮動小数点積和演算器のための回路分割手法を検討する．演算器内の部分積生成部，部分積圧縮部，およびシフタに着目した回路分割手法を提案し，提案手法に基づいて三次元積層型浮動小数点積和演算器を設計し性能を評価する．回路シミュレータによる評価の結果，提案手法を用いて設計された三次元積層型倍精度浮動小数点積和演算器は，二次元実装の場合と比較して最大 21.7％の高速化を達成した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point fused multiply-add unit, this paper discusses and proposes circuit partitioning methods for a floating point fused multiply-add unit. The proposed methods focus on the partial product generator, the partial product reduction tree, and the shifter. Experimental results show the 3-D stacked fused multiply-add unit which is designed based on the proposed partitioning method achieves a 21.7% critical path delay reduction compared to the 2-D implementation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-10-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2015-SLDM-172"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}