{"links":{},"id":144740,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144740","sets":["581:7706:7714"]},"path":["7714"],"owner":"11","recid":"144740","title":["System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-08-15"},"_buckets":{"deposit":"bd8535c7-fd78-41e4-b290-55929520bfe2"},"_deposit":{"id":"144740","pid":{"type":"depid","value":"144740","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler","author_link":["219870","219871","219873","219872","219875","219868","219869","219874"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler"},{"subitem_title":"System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[特集：組込みシステム工学] hardware/software co-design, design environments, design space exploration, interrupt handling","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2015-08-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"publish_status":"0","weko_shared_id":11,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144740/files/IPSJ-JNL5608003.pdf","label":"IPSJ-JNL5608003.pdf"},"date":[{"dateType":"Available","dateValue":"2017-08-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL5608003.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"202663b3-0ae0-4d0f-b775-a03bd88e66d5","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuki, Ando"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Honda"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Takada"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masato, Edahiro"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuki, Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Honda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masato, Edahiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.\n\\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.23(2015) No.5 (online)\n------------------------------","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.\n\\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.23(2015) No.5 (online)\n------------------------------","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicIssueDates":{"bibliographicIssueDate":"2015-08-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"56"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:20:29.143698+00:00","updated":"2025-01-20T06:43:23.963776+00:00"}