| Item type |
Trans(1) |
| 公開日 |
2015-08-01 |
| タイトル |
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タイトル |
A 3D FPGA Architecture to Realize Simple Die Stacking |
| タイトル |
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言語 |
en |
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タイトル |
A 3D FPGA Architecture to Realize Simple Die Stacking |
| 言語 |
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言語 |
eng |
| キーワード |
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主題Scheme |
Other |
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主題 |
[Emerging Technology] 3D FPGA, spatially distributed type, functionally distributed type |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
| 著者所属 |
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Kumamoto University |
| 著者所属 |
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Kumamoto University |
| 著者所属 |
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Kumamoto University |
| 著者所属 |
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Kumamoto University |
| 著者所属 |
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Kumamoto University |
| 著者所属(英) |
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en |
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Kumamoto University |
| 著者所属(英) |
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en |
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Kumamoto University |
| 著者所属(英) |
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en |
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Kumamoto University |
| 著者所属(英) |
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en |
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Kumamoto University |
| 著者所属(英) |
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en |
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Kumamoto University |
| 著者名 |
Motoki, Amagasaki
Qian, Zhao
Masahiro, Iida
Morihiro, Kuga
Toshinori, Sueyoshi
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| 著者名(英) |
Motoki, Amagasaki
Qian, Zhao
Masahiro, Iida
Morihiro, Kuga
Toshinori, Sueyoshi
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| 論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
To balance between cost and performance, and to explore 3D field-programmable gate array (FPGA) with realistic 3D integration processes, we propose spatially distributed and functionally distributed types of 3D FPGA architectures. The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology. Since vertical wires pass through microbumps, no TSVs are needed. In contrast, the spatially distributed architecture is divided into multiple layers with the same structure, unlike in the functionally distributed type. This architecture can be expanded to more than two layers by stacking multiples of the same die. The goal of this paper is to elucidate the advantages and disadvantages of these two types of 3D FPGAs. According to our evaluation, when only two layers are used, the functionally distributed architecture is more effective. When higher performance is achieved by using more than two layers, the spatially distributed architecture achieves better performance. |
| 論文抄録(英) |
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内容記述タイプ |
Other |
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内容記述 |
To balance between cost and performance, and to explore 3D field-programmable gate array (FPGA) with realistic 3D integration processes, we propose spatially distributed and functionally distributed types of 3D FPGA architectures. The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology. Since vertical wires pass through microbumps, no TSVs are needed. In contrast, the spatially distributed architecture is divided into multiple layers with the same structure, unlike in the functionally distributed type. This architecture can be expanded to more than two layers by stacking multiples of the same die. The goal of this paper is to elucidate the advantages and disadvantages of these two types of 3D FPGAs. According to our evaluation, when only two layers are used, the functionally distributed architecture is more effective. When higher performance is achieved by using more than two layers, the spatially distributed architecture achieves better performance. |
| 書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA12394951 |
| 書誌情報 |
IPSJ Transactions on System LSI Design Methodology （TSLDM）
巻 8,
p. 116-122,
発行日 2015-08-01
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| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
1882-6687 |
| 出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |
IPSJ-TSLDM0800014.pdf (902.0 kB)
