{"updated":"2025-01-20T18:43:38.887594+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144668","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"144668","title":["Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-08-01"},"_buckets":{"deposit":"5447facc-5d41-4790-902d-913da91c74d2"},"_deposit":{"id":"144668","pid":{"type":"depid","value":"144668","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip","author_link":["219577","219569","219573","219568","219571","219572","219574","219570","219576","219575"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip"},{"subitem_title":"Automatic Synthesis of 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University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144668/files/IPSJ-TSLDM0800011.pdf","label":"IPSJ-TSLDM0800011.pdf"},"date":[{"dateType":"Available","dateValue":"2015-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800011.pdf","filesize":[{"value":"777.2 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PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"99","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"95","bibliographicIssueDates":{"bibliographicIssueDate":"2015-08-01","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:20:25.373931+00:00","id":144668,"links":{}}