Item type |
Trans(1) |
公開日 |
2015-08-01 |
タイトル |
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タイトル |
A Performance Enhanced Dual-switch Network-on-chip Architecture |
タイトル |
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言語 |
en |
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タイトル |
A Performance Enhanced Dual-switch Network-on-chip Architecture |
言語 |
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言語 |
eng |
キーワード |
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主題Scheme |
Other |
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主題 |
[Architectural Design] network-on-chip, dual-switch, performance enhanced |
資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
著者所属 |
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Graduate School of Information, Production and Systems, Waseda University |
著者所属 |
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Graduate School of Information, Production and Systems, Waseda University |
著者所属 |
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Graduate School of Information, Production and Systems, Waseda University |
著者所属(英) |
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en |
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Graduate School of Information, Production and Systems, Waseda University |
著者所属(英) |
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en |
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Graduate School of Information, Production and Systems, Waseda University |
著者所属(英) |
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en |
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Graduate School of Information, Production and Systems, Waseda University |
著者名 |
Lian, Zeng
Xin, Jiang
Takahiro, Watanabe
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著者名(英) |
Lian, Zeng
Xin, Jiang
Takahiro, Watanabe
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論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
With rapid progress in semiconductor technology, Network-on-Chip (NoC) becomes an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. The delay of router and packets contention can significantly affect network latency and throughput. As the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing DSA design, we can make utmost use of idle output ports to reduce packets contention delay, meanwhile, without increasing router delay. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power and area overhead. |
論文抄録(英) |
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内容記述タイプ |
Other |
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内容記述 |
With rapid progress in semiconductor technology, Network-on-Chip (NoC) becomes an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. The delay of router and packets contention can significantly affect network latency and throughput. As the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing DSA design, we can make utmost use of idle output ports to reduce packets contention delay, meanwhile, without increasing router delay. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power and area overhead. |
書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA12394951 |
書誌情報 |
IPSJ Transactions on System LSI Design Methodology (TSLDM)
巻 8,
p. 85-94,
発行日 2015-08-01
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ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
1882-6687 |
出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |