{"updated":"2025-01-20T18:43:35.553543+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144666","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"144666","title":["Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-08-01"},"_buckets":{"deposit":"251dac57-3ecd-4705-ba37-cae0f6169064"},"_deposit":{"id":"144666","pid":{"type":"depid","value":"144666","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design","author_link":["219556","219560","219559","219558","219554","219555","219561","219557"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design"},{"subitem_title":"Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Physical Design] PCB routing, equal-length routing, single commodity flow, EDA","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2015-08-01","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information, Production and Systems, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144666/files/IPSJ-TSLDM0800009.pdf","label":"IPSJ-TSLDM0800009.pdf"},"date":[{"dateType":"Available","dateValue":"2015-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800009.pdf","filesize":[{"value":"3.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"01c283dc-dd3f-45f4-ae82-4eb62778d318","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ran, Zhang"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tieyuan, Pan"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Li, Zhu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahiro, Watanabe"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ran, Zhang","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tieyuan, Pan","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Li, Zhu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahiro, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"84","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"75","bibliographicIssueDates":{"bibliographicIssueDate":"2015-08-01","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:20:25.269196+00:00","id":144666,"links":{}}