@article{oai:ipsj.ixsq.nii.ac.jp:00144666,
 author = {Ran, Zhang and Tieyuan, Pan and Li, Zhu and Takahiro, Watanabe and Ran, Zhang and Tieyuan, Pan and Li, Zhu and Takahiro, Watanabe},
 journal = {IPSJ Transactions on System LSI Design Methodology （TSLDM）},
 month = {Aug},
 note = {In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times., In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.},
 pages = {75--84},
 title = {Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design},
 volume = {8},
 year = {2015}
}