{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144664","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"144664","title":["Heterogeneous Multi-core Architectures"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-08-01"},"_buckets":{"deposit":"1d76aa7c-49d2-4036-a582-e452ab21ce19"},"_deposit":{"id":"144664","pid":{"type":"depid","value":"144664","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Heterogeneous Multi-core Architectures","author_link":["219546","219547"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Heterogeneous Multi-core Architectures"},{"subitem_title":"Heterogeneous Multi-core Architectures","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Architectural Design] heterogeneous multi-core, CPU, GPU, special-purpose accelerator, reconfigurable computing","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2015-08-01","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"School of Computing, National University of Singapore"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Computing, National University of Singapore","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144664/files/IPSJ-TSLDM0800007.pdf","label":"IPSJ-TSLDM0800007.pdf"},"date":[{"dateType":"Available","dateValue":"2015-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800007.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"bd44d572-1249-41f9-b128-780d394ef235","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tulika, Mitra"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tulika, Mitra","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"62","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"51","bibliographicIssueDates":{"bibliographicIssueDate":"2015-08-01","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":144664,"updated":"2025-01-20T18:43:33.288231+00:00","links":{},"created":"2025-01-19T00:20:25.164455+00:00"}