Heterogeneous Multi-core Architectures

• Item type: Trans(1)
• 公開日: 2015-08-01
• タイトル: Heterogeneous Multi-core Architectures
• タイトル / 言語: en
• タイトル: Heterogeneous Multi-core Architectures
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Architectural Design] heterogeneous multi-core, CPU, GPU, special-purpose accelerator, reconfigurable computing
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: School of Computing, National University of Singapore
• 著者所属(英): en
• 著者所属(英): School of Computing, National University of Singapore
• 著者名: Tulika, Mitra
• 著者名(英): Tulika, Mitra
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 8, p. 51-62, 発行日 2015-08-01
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会