{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144539","sets":["1164:1579:7841:8311"]},"path":["8311"],"owner":"11","recid":"144539","title":["ニアメモリ処理アーキテクチャのFPGAヘの実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-07-28"},"_buckets":{"deposit":"3aa8f1b7-1080-4478-92ff-ea99353e8a21"},"_deposit":{"id":"144539","pid":{"type":"depid","value":"144539","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ニアメモリ処理アーキテクチャのFPGAヘの実装と評価","author_link":["218893","218898","218894","218897","218896","218895","218892","218899"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ニアメモリ処理アーキテクチャのFPGAヘの実装と評価"},{"subitem_title":"Implementation and Evaluation of Near Memory Processing Architecture on FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"専用ハードウェア","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-07-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144539/files/IPSJ-ARC15216006.pdf","label":"IPSJ-ARC15216006.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC15216006.pdf","filesize":[{"value":"431.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"cd3e4eb7-dd4b-4c5d-9a2a-3a54bdc18b8f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"枝元, 正寛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tran, Thi Hong"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高前田, 伸也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中島, 康彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tadahiro, Edamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Thi, Hong Tran","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Takamaeda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasuhiko, Nakashima","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"データ移動に起因する消費電力の削減とメモリ帯域の活用を目的に，メインメモリの近くで演算を行うニアメモリ処理アーキテクチャが注目されている本論文では，ニアメモリ処理プロセッサのハードウェア構成およびソフトウェアモデルの検討のために，FPGA を用いたプロトタイピングシステムを開発し評価する．まず，ニアメモリ処理プロセッサの設計検証を加速するために，バスインターフェースを抽象化し，少ない HDL 記述で IP コアを自動生成する新しいフレームワークを開発した．次に，ARM プロセッサを搭載する FPGA 上に，初期検討として，MIPS ISA を持つインオーダコアとメモリシステム及び制御機構をニアメモリ処理プロセッサとして実装した．その上に，ニアメモリ処理プロセッサと汎用コアの連携を可能にする C ベースのプログラミングモデルおよびライブラリを実装した．小規模なアプリケーションを用いた評価の結果，提案するプロトタイピングシステムが FPGA 実機上で正しく動作することを確認したしかし，実験に用いたインオーダコアではメモリ帯域の活用と遅延の隠蔽が十分でないため，性能向上を達成できなかった．このことから，メモリ帯域を活用するためのメモリ密結合型 SIMD 機構や，メモリアクセス遅延を隠蔽するための演算とメモリアクセスのオーバーラッピング手法などが必要であることが明らかになった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The main bottleneck of microprocessors is the amount of available power budget per chip. Additionally, energy consumption for data movements will become much larger than the one for computing, by the further transistor scaling. High performance and power consumption is achieved by using cache memory in conventional processer system. However, in graph processing that is gaining attention for broad applicability has much size of data and irregular memory access patterns. It is hard to achieve good performance due not to utilize cache memory can ' t enclose much amount of data. There is a concept that Near Data Processing could overcome this problem to reduce energy for transferring data from main memory to processer. In this paper, we propose a near data processing architecture as a prototype, its implimentation method and high level abstracted programming model for this architecture.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-07-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2015-ARC-216"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T00:20:18.640404+00:00","updated":"2025-01-20T12:53:52.431970+00:00","id":144539}