{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00144534","sets":["1164:1579:7841:8311"]},"path":["8311"],"owner":"11","recid":"144534","title":["GAを用いたNoCの最適設計探索"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-07-28"},"_buckets":{"deposit":"daf67b6b-ec92-4c63-8973-2d2c6689bf89"},"_deposit":{"id":"144534","pid":{"type":"depid","value":"144534","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"GAを用いたNoCの最適設計探索","author_link":["218867","218868","218869","218870"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"GAを用いたNoCの最適設計探索"},{"subitem_title":"The Network-on-Chip Optimization By Using Of Genetic Algorithm","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ設計探索","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-07-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/144534/files/IPSJ-ARC15216001.pdf","label":"IPSJ-ARC15216001.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC15216001.pdf","filesize":[{"value":"408.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"64b65867-73a2-4393-8806-fba6126e2d9b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"村上, 太一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Daichi, Murakami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kei, Hiraki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Hetero-NoC は近年提案された NoC の設計方法であり，通常の NoC と同じ消費電力・資源量のままに，より小さいレイテンシを実現するものである．Hetero-NoC の設計においては，高性能・低性能 2 種類のコンポーネントを適切に配置することが求められる．しかしながら現在までに提案されている配置は，現実には存在しないような簡易化された NoC におけるトラフィックの性質に頼ったものであり，より複雑な，現実に存在するような NoC に適用した場合にも有効であるかはについては，考察の余地を残している．複雑な NoC において，最適な配置を定性的な性質から求める方法は確立されておらず，また，困難であることが予想される．本研究ではシミュレーションと遺伝的アルゴリズムを用いて，Hetero-NoC におけるコンポーネントを配置の最適化を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Hetero-NoC is a new design of Network-on-Chip (NoC) which acheives lower latency without increasing the amount of resources. In Hetero-NoC's design, two different sizes of components should be arranged properly. Previous arrangements, however, depend on the center-oriented traffic property which is seen in only simple NoC, so it is suspicious that these arrangements could benefit the real NoC which is often more complex. In addition, the method of designing Hetero-NoC from its qualitative aspects is not formalized yet and predicated to be difficult be cause of many factors in NoC like the location of memory controller, routing algorithm, and so on. In this research, we optimized the arrangements of the NoC's components by using of NoC simulation and genetic algorithm.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-07-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2015-ARC-216"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":144534,"updated":"2025-01-20T12:54:00.556649+00:00","links":{},"created":"2025-01-19T00:20:18.382196+00:00"}