{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00014264","sets":["581:768:777"]},"path":["777"],"owner":"1","recid":"14264","title":["汎用エンジンRM - IIの構成"],"pubdate":{"attribute_name":"公開日","attribute_value":"1994-04-15"},"_buckets":{"deposit":"87b2af40-1a2b-4dd7-8348-16353e7cdd8e"},"_deposit":{"id":"14264","pid":{"type":"depid","value":"14264","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"汎用エンジンRM - IIの構成","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"汎用エンジンRM - IIの構成"},{"subitem_title":"A Reconfigurable Machine : RM - II","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：並列処理","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1994-04-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"神戸大学大学院自然科学研究科"},{"subitem_text_value":"神戸大学大学院自然科学研究科"},{"subitem_text_value":"神戸大学大学院自然科学研究科"},{"subitem_text_value":"神戸大学大学院自然科学研究科"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The Graduate School of Science and Technology, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"The Graduate School of Science and Technology, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"The Graduate School of Science and Technology, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"The Graduate School of Science and Technology, Kobe University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/14264/files/IPSJ-JNL3504016.pdf"},"date":[{"dateType":"Available","dateValue":"1996-04-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3504016.pdf","filesize":[{"value":"994.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"08fe9855-cc0d-4276-bf2c-141a15200b59","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1994 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"冨田, 昌宏"},{"creatorName":"澄川, 文徳"},{"creatorName":"菅沼, 直昭"},{"creatorName":"平野, 浩太郎"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masahiro, Tomita","creatorNameLang":"en"},{"creatorName":"Fuminori, Sumikawa","creatorNameLang":"en"},{"creatorName":"Naoaki, Suganuma","creatorNameLang":"en"},{"creatorName":"Kotaro, Hirano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"電気的に書替え可能なFPGAをメモリと組み合せることによって、複数の用途への適用を可能とする帆用エンジンの概念に墓づいて開発されたRM?II（Reconfgurable Machine-II）について述べる. 汎用エンジンは、FPGA上に実現するワイヤード論理によって専用エンジンに近い性能を得る一方で、複数の応用に対応可能である点に特徴をもつ。最初のプロトタイプであるRM?Iに右いて問題となった規模と柔軟性の不足を解決することをRM?II開発の主眼とした。実現可能な回路規模およびメモリ容量を倍増させるとともに、FPGA間の配線を変更するためのFPGAの導入によって柔軟性を高めた。通常は一つのCPUで行う処理を複数のFPGAに分割して実現することが一般的な汎用エンジンでは、データパスが複数のFPGAにまたがることが多く、多様な通信を短時間で完了する必要がある。さらに、FPGAの外部端子数に関する制約も厳しい。そこで、FPGAとメモリの接続糠を流用してX／Y方向のバスと接続するクロスバスを導入することで、多様な転送を多くの場含1クロックで実現した。論理シミュレーション、論理設計誤りの診断と画像処理に適用した、その結果、RM?Iの約2倍の性能が得られることを確認した。","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"645","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"636","bibliographicIssueDates":{"bibliographicIssueDate":"1994-04-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4","bibliographicVolumeNumber":"35"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"可変構造アーキテクチャ"}]},"weko_creator_id":"1"},"id":14264,"updated":"2025-01-23T00:53:15.982073+00:00","links":{},"created":"2025-01-18T22:48:07.661048+00:00"}