{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00014061","sets":["581:768:769"]},"path":["769"],"owner":"1","recid":"14061","title":["Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination"],"pubdate":{"attribute_name":"公開日","attribute_value":"1994-12-15"},"_buckets":{"deposit":"9e4d7a08-c3fb-4e92-acfd-f4ae9a65a5cd"},"_deposit":{"id":"14061","pid":{"type":"depid","value":"14061","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination"},{"subitem_title":"Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1994-12-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Energy Research Laboratory  Hitachi  Ltd 7 -2- 1 Omika - cho  Hitachi  Ibaraki  316"},{"subitem_text_value":"Systems Engineering Division  Hitachi  Ltd 6 Kanda - surugadai 4 chome  Chiyoda - ku  Tokyo 101"},{"subitem_text_value":"Systems Engineering Division  Hitachi  Ltd 6 Kanda - surugadai 4 chome  Chiyoda - ku  Tokyo 101"},{"subitem_text_value":"Kokubu Works  Hitachi  Ltd 1 - 1 Kokubo - cho  1chome  Hitachi  Ibaraki 316"},{"subitem_text_value":"Computer & Communication Research Center  The Tokyo Electric Power Co. 1 -4- 10 Irifune  Chuo - ku  Tokyo 104"},{"subitem_text_value":"Computer & Communication Research Center  The Tokyo Electric Power Co. 1 -4- 10 Irifune  Chuo - ku  Tokyo 104"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Energy Research Laboratory, Hitachi, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Systems Engineering Division, Hitachi, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Systems Engineering Division, Hitachi, Ltd 6 Kanda - surugadai 4 chome, Chiyoda - ku, Tokyo 101","subitem_text_language":"en"},{"subitem_text_value":"Kokubu Works, Hitachi, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Computer & Communication Research Center, The Tokyo Electric Power Co","subitem_text_language":"en"},{"subitem_text_value":"Computer & Communication Research Center, The Tokyo Electric Power Co","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/14061/files/IPSJ-JNL3512025.pdf"},"date":[{"dateType":"Available","dateValue":"1996-12-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3512025.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"efe624ce-cc6d-42bb-a349-be0ec6846288","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1994 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Naoyuki, Yamada"},{"creatorName":"Yoshikatsu, Ueda"},{"creatorName":"Junko, Ito"},{"creatorName":"Tomoharu, Nakamura"},{"creatorName":"Junichi, Yoshizawa"},{"creatorName":"Satoshi, Matsuda"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Naoyuki, Yamada","creatorNameLang":"en"},{"creatorName":"Yoshikatsu, Ueda","creatorNameLang":"en"},{"creatorName":"Junko, Ito","creatorNameLang":"en"},{"creatorName":"Tomoharu, Nakamura","creatorNameLang":"en"},{"creatorName":"Junichi, Yoshizawa","creatorNameLang":"en"},{"creatorName":"Satoshi, Matsuda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"A design verification method for sequential control circuits with timing coordination has been developed. Unlike prevailing numeric simulations  this method is based on a theorem-proving technique. Sequential control circuits realize their target functions by coordinating the asyn-chronously inputted signals. In order to verify timing coordination efnciently  the control strategy which combines hyperresolution and a connection graph method with attached procedures for handling time variables symbolically has been developed. This method facilitates not only the verification of timing coordination but also the extraction of intended behavlours from proposed designs. The developed method was applied to verificatlon of an auto-reclosing circuit in an electric power substatlon which contains about 40 components. The verification for each specification was executed correctly In about I minute on a mainframe computer. The developed verification method was judged to be useful and efficient for practical use.","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A design verification method for sequential control circuits with timing coordination has been developed. Unlike prevailing numeric simulations, this method is based on a theorem-proving technique. Sequential control circuits realize their target functions by coordinating the asyn-chronously inputted signals. In order to verify timing coordination efnciently, the control strategy which combines hyperresolution and a connection graph method with attached procedures for handling time variables symbolically has been developed. This method facilitates not only the verification of timing coordination but also the extraction of intended behavlours from proposed designs. The developed method was applied to verificatlon of an auto-reclosing circuit in an electric power substatlon which contains about 40 components. The verification for each specification was executed correctly In about I minute on a mainframe computer. The developed verification method was judged to be useful and efficient for practical use.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"2784","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"2774","bibliographicIssueDates":{"bibliographicIssueDate":"1994-12-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicVolumeNumber":"35"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"ハードウェア設計"}]},"weko_creator_id":"1"},"updated":"2025-01-23T00:58:45.443896+00:00","created":"2025-01-18T22:47:58.767216+00:00","id":14061}