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Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination
https://ipsj.ixsq.nii.ac.jp/records/14061
https://ipsj.ixsq.nii.ac.jp/records/1406129e08317-aacc-41e0-86d0-dffafaa6fa23
| 名前 / ファイル | ライセンス | アクション |
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Copyright (c) 1994 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | Journal(1) | |||||||
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| 公開日 | 1994-12-15 | |||||||
| タイトル | ||||||||
| タイトル | Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Design Verification Based on Theorem - Proving Technique for Sequential Control Circuits with Timing Coordination | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | 論文 | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| その他タイトル | ||||||||
| その他のタイトル | ハードウェア設計 | |||||||
| 著者所属 | ||||||||
| Energy Research Laboratory Hitachi Ltd 7 -2- 1 Omika - cho Hitachi Ibaraki 316 | ||||||||
| 著者所属 | ||||||||
| Systems Engineering Division Hitachi Ltd 6 Kanda - surugadai 4 chome Chiyoda - ku Tokyo 101 | ||||||||
| 著者所属 | ||||||||
| Systems Engineering Division Hitachi Ltd 6 Kanda - surugadai 4 chome Chiyoda - ku Tokyo 101 | ||||||||
| 著者所属 | ||||||||
| Kokubu Works Hitachi Ltd 1 - 1 Kokubo - cho 1chome Hitachi Ibaraki 316 | ||||||||
| 著者所属 | ||||||||
| Computer & Communication Research Center The Tokyo Electric Power Co. 1 -4- 10 Irifune Chuo - ku Tokyo 104 | ||||||||
| 著者所属 | ||||||||
| Computer & Communication Research Center The Tokyo Electric Power Co. 1 -4- 10 Irifune Chuo - ku Tokyo 104 | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Energy Research Laboratory, Hitachi, Ltd | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Systems Engineering Division, Hitachi, Ltd | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Systems Engineering Division, Hitachi, Ltd 6 Kanda - surugadai 4 chome, Chiyoda - ku, Tokyo 101 | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Kokubu Works, Hitachi, Ltd | ||||||||
| 著者所属(英) | ||||||||
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| Computer & Communication Research Center, The Tokyo Electric Power Co | ||||||||
| 著者所属(英) | ||||||||
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| Computer & Communication Research Center, The Tokyo Electric Power Co | ||||||||
| 著者名 |
Naoyuki, Yamada
Yoshikatsu, Ueda
Junko, Ito
Tomoharu, Nakamura
Junichi, Yoshizawa
Satoshi, Matsuda
× Naoyuki, Yamada Yoshikatsu, Ueda Junko, Ito Tomoharu, Nakamura Junichi, Yoshizawa Satoshi, Matsuda
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| 著者名(英) |
Naoyuki, Yamada
Yoshikatsu, Ueda
Junko, Ito
Tomoharu, Nakamura
Junichi, Yoshizawa
Satoshi, Matsuda
× Naoyuki, Yamada Yoshikatsu, Ueda Junko, Ito Tomoharu, Nakamura Junichi, Yoshizawa Satoshi, Matsuda
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A design verification method for sequential control circuits with timing coordination has been developed. Unlike prevailing numeric simulations this method is based on a theorem-proving technique. Sequential control circuits realize their target functions by coordinating the asyn-chronously inputted signals. In order to verify timing coordination efnciently the control strategy which combines hyperresolution and a connection graph method with attached procedures for handling time variables symbolically has been developed. This method facilitates not only the verification of timing coordination but also the extraction of intended behavlours from proposed designs. The developed method was applied to verificatlon of an auto-reclosing circuit in an electric power substatlon which contains about 40 components. The verification for each specification was executed correctly In about I minute on a mainframe computer. The developed verification method was judged to be useful and efficient for practical use. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | A design verification method for sequential control circuits with timing coordination has been developed. Unlike prevailing numeric simulations, this method is based on a theorem-proving technique. Sequential control circuits realize their target functions by coordinating the asyn-chronously inputted signals. In order to verify timing coordination efnciently, the control strategy which combines hyperresolution and a connection graph method with attached procedures for handling time variables symbolically has been developed. This method facilitates not only the verification of timing coordination but also the extraction of intended behavlours from proposed designs. The developed method was applied to verificatlon of an auto-reclosing circuit in an electric power substatlon which contains about 40 components. The verification for each specification was executed correctly In about I minute on a mainframe computer. The developed verification method was judged to be useful and efficient for practical use. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AN00116647 | |||||||
| 書誌情報 |
情報処理学会論文誌 巻 35, 号 12, p. 2774-2784, 発行日 1994-12-15 |
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| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-7764 | |||||||