{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00013530","sets":["581:742:743"]},"path":["743"],"owner":"1","recid":"13530","title":["超並列計算機におけるマルチスレッド処理機構と基本性能"],"pubdate":{"attribute_name":"公開日","attribute_value":"1996-12-15"},"_buckets":{"deposit":"13a0b4c0-9f96-44c0-83c0-6a8db04fab8d"},"_deposit":{"id":"13530","pid":{"type":"depid","value":"13530","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"超並列計算機におけるマルチスレッド処理機構と基本性能","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"超並列計算機におけるマルチスレッド処理機構と基本性能"},{"subitem_title":"Multithread Execution Mechanisms on a Massively Parallel Computer","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1996-12-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"新情報処理開発機構"},{"subitem_text_value":"新情報処理開発機構"},{"subitem_text_value":"新情報処理開発機構"},{"subitem_text_value":"新情報処理開発機構"},{"subitem_text_value":"筑波大学"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Real World Computing Partnership","subitem_text_language":"en"},{"subitem_text_value":"Real World Computing Partnership","subitem_text_language":"en"},{"subitem_text_value":"Real World Computing Partnership","subitem_text_language":"en"},{"subitem_text_value":"Real World Computing Partnership","subitem_text_language":"en"},{"subitem_text_value":"Universitiy of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/13530/files/IPSJ-JNL3712024.pdf"},"date":[{"dateType":"Available","dateValue":"1998-12-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3712024.pdf","filesize":[{"value":"876.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"678d123a-18bf-4244-9bd8-5a16b5a8f989","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1996 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"岡本, 一晃"},{"creatorName":"松岡, 浩司"},{"creatorName":"廣野, 英雄"},{"creatorName":"横田, 隆史"},{"creatorName":"坂井, 修一"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazuaki, Okamoto","creatorNameLang":"en"},{"creatorName":"Hiroshi, Matsuoka","creatorNameLang":"en"},{"creatorName":"Hideo, Hirono","creatorNameLang":"en"},{"creatorName":"Takashi, Yokota","creatorNameLang":"en"},{"creatorName":"Shuichi, Sakai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"超並列計算機においては  遠隔メモリ操作や遠隔手続き呼び出しにともなうレイテンシが大きな問題となる. これを解決する手段として  マルチスレッド処理によるレイテンシの隠蔽があげられる. さまざまな粒度におけるマルチスレッド処理を効率良く実行するためには  効果的なハードウェアによる支援が期待できるようなスレッド処理機構を  プロセッサが備える必要がある. 本稿では  効率良くマルチスレッド処理を実行するスレッド処理機構について考え  超並列計算機向けのプロセッサアーキテクチャを示す. そしてこれに基づいて現在開発中の  マルチスレッド型プロセッサRICA-1を紹介し  その基本性能を示す. また  遠隔メモリ操作や遠隔手続き呼び出しなどが  マルチスレッド処理によるレイテンシ隠蔽によって  効率良く実現できることを示す.","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Latencies of remote memory access and remote procedure call are serious problems on a massively parallel computer. In order to improve the machine performance, it is quite effective to hide these latencies by multithreading. Thread execution mechanism which is effectively supported by the hardware is indispensable to realize efficient multithread execution. In this paper, we propose the processor architecture for massively parallel computers with efficient thread execution mechanism, and present RICA-1 multithreaded processor based on it. On the RICA-1, both remote memory access and remote procedure call are realized efficiently.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"2407","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"2398","bibliographicIssueDates":{"bibliographicIssueDate":"1996-12-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicVolumeNumber":"37"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"並列処理"}]},"weko_creator_id":"1"},"id":13530,"updated":"2025-01-23T01:12:38.912673+00:00","links":{},"created":"2025-01-18T22:47:35.500825+00:00"}