{"created":"2025-01-18T22:47:32.779171+00:00","updated":"2025-01-23T01:14:27.469413+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00013469","sets":["581:729:739"]},"path":["739"],"owner":"1","recid":"13469","title":["3層チャネルレス・ゲートアレイのための高速配線手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1997-03-15"},"_buckets":{"deposit":"291c6b9e-28ef-4536-8fbe-28fcfee4bb68"},"_deposit":{"id":"13469","pid":{"type":"depid","value":"13469","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"3層チャネルレス・ゲートアレイのための高速配線手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"3層チャネルレス・ゲートアレイのための高速配線手法"},{"subitem_title":"A Fast Routing Method for Channel - less Sea -of- gates Arrays with Three Routing Layers","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1997-03-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三菱電機株式会社半導体基盤技術統括部"},{"subitem_text_value":"三菱電機株式会社半導体基盤技術統括部"},{"subitem_text_value":"三菱電機株式会社半導体基盤技術統括部"},{"subitem_text_value":"三菱電機セミコンダクタソフトウェア株式会社"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Manufacturing Technology Division, Semiconductor Group, Mitsubishi Electric Corporation","subitem_text_language":"en"},{"subitem_text_value":"Manufacturing Technology Division, Semiconductor Group, Mitsubishi Electric Corporation","subitem_text_language":"en"},{"subitem_text_value":"Manufacturing Technology Division, Semiconductor Group, Mitsubishi Electric Corporation","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Semiconductor Software Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/13469/files/IPSJ-JNL3803028.pdf"},"date":[{"dateType":"Available","dateValue":"1999-03-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3803028.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d352ebea-cb9e-4e58-8392-855014509b4d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1997 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"寺井, 正幸"},{"creatorName":"城田, 博史"},{"creatorName":"柴谷, 聡"},{"creatorName":"佐藤興二"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masayuki, Terai","creatorNameLang":"en"},{"creatorName":"Hiroshi, Shirota","creatorNameLang":"en"},{"creatorName":"Satoshi, Shibatani","creatorNameLang":"en"},{"creatorName":"Koji, Sato","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"3層配線チャネルレスCMOSシー・オブ・ゲートアレイ用高速自動配線手法について報告する．本手法は，SOGのレイアウト構造の規則性に着目してセル列単位で配線を行うもので，独自の“over?the?cell”チャネルルータを基本としている．このため，セル列間に配線チャネルを設けないチャネルレス方式で配置されたセルの端子間の配線要求を扱う本手法の詳細配線処理の計算複雑度がO (n・plogp）である（p：1セル列上の端子数の最大値，n：チップ上のセル列数）．これは，チャネル有方式のレイアウトに対する代表的なチャネルルータによる配線処理の計算複雑度と等しい．実際のSOG回路とよく知られたベンチマークデータを用いた実験を行い，この結果から，本手法の高速性と有効性を示す．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A fast routing method for CMOS triple-metal-layer sea-of-gates(SOG) arrays is reported.The method efficiently utilizes the regularity in layout structures of channel-less SOG chips,and employs our own over-the-cell channel router.Although it handles channel-less layout structures,the time complexity of the detailed routing algorithm of the proposed method is O(n・plog p),where p is the maximum number of terminals in a cell row,and n is the number of rows of cells in the chip.The time complexity is equal to that of typical channel routing in a channeled layout.The effectiveness of our method is demonstrated by our experimental results on industrial SOG chips and a well-known benchmark circuit.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"668","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"657","bibliographicIssueDates":{"bibliographicIssueDate":"1997-03-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"38"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"ハードウェア"}]},"weko_creator_id":"1"},"id":13469,"links":{}}